PMK dynamic and leakage power reduction are proven in silicon on ARM Physical IP test silicon as well as on ARM processor designs.
Dynamic power can be reduced by lowering the operation voltage for the entire chip or blocks; different on-chip voltage islands require the use of level shifters
Leakage power can be dramatically reduced by powering down blocks of the chips, this is can be achieved by on-chip power gates by switching power (VDD) or ground (VSS)
- If powering down parts of the chip, it may be necessary to maintain the state of sequential elements: this is supported via retention flip-flops, retention scan flip-flops and retention latches
