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ARM® Single Port and Dual Port SRAM memory compilers are available in a variety of different architectures that support wide performance range for all types of SoC designs. Designers can choose from High density, High Speed and Low Power SRAMs to optimize their design for speed, power and/or area. ARM SRAM memory compilers are available in over 15 different foundries and 65 process variants from 28nm to 250nm.

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SRAM Memory is for the temporary storage of large quantities of information. Available in 1-Port and 2-Port versions ARM SRAM memory IP typically finds usage in L2/L3 cache solutions, temporary buffers or wherever larger memory instances are required in an SoC design.
  • High Speed memories for performance critical designs
  • High Density memories for mainstream and cost critical applications
  • Low Power memories for battery operated portable applications.
  • Broad support for all leading EDA vendors ensuring quick time to market
  • Flexible business models like ‘free library program’ and ‘try before you buy’ allowing lowest cost of ownership
  • Memory sub-circuits optimized over multiple sub ranges to provide power, performance and area close to a custom design.

Wide performance range for all types of designs

           Sub Range Optimisation

  • Lowest risk solutions with ARM memories being used by IDMs, fabless start-ups, IC companies and IDMs backed up by a knowledgeable customer support team available in multiple time zones

  • Several choices of High Speed and High Density memories are available based on bank size, bit-cell choice, Vt implant and low voltage operation.
  • High Speed memories are for performance critical designs that can range up to 2.5 GHz range at 28 nm technology. High Speed memories are on average 30% faster than High Density memories.

                        Speed Vs Density Performance

  • High Density memories are 30% smaller compared to High speed memories and designed for high array efficiency. Targeted for mainstream and cost sensitive applications, these memories can achieve up to 7000 Kbit/mm² at 28 nm technology

                        Speed Vs Density Memory Area

  • Low Power memories reduce leakage current by up to 30% over the standard memories. These memories are targeted for power sensitive handheld markets.
  • Multiple power management modes available providing up to 20x reduction in leakage in power down mode over the regular standby mode

                       Relative Power Savings                        


Depending upon foundry, geometry and process variant memory compilers support multiple features to ensure optimal implementation of all types of designs.


Key Features Benefits
Multiple architectures with flexibility to tradeoff density/performance Minimize die area and reduce die cost
Multiple Power management modes with power gating and multi-voltage operation Flexible power management allows packaging cost reduction, competitive product with higher battery life 
Comprehensive redundancy scheme Enables yield optimization
Flexible margining features Allow yield/performance tradeoff
Optional integrated pipeline Allow high throughput
Soft error repair Enables yield optimization
Advanced test features Enhance product quality and minimize field returns
Pseudo scan Cuts down test time drastically by orders of magnitude reducing overall product test cost significantly
Improved product quality lowers field failure


  • Power grid supported at all the advance nodes as well as any new mainstream geometries. Multiple options for power rings supported in mature nodes.
  • Use of up to, and including, metal 3/4, depending upon compiler.
  • Flexible write mask options for partitioning bits and reducing read/write power.


32 nm SRAM Memory Compilers

Memory Solution Architecture Maximum Size Mux Options

Single Port SRAM

High Speed

576 Kbits 

4, 8, 16, 32

Single Port SRAM

High Density

1152 Kbits

8, 16, 32

Dual Port SRAM

High Density

320 Kbits 

4, 8, 16


40/45 nm SRAM Memory Compilers

Memory Solution Architecture Maximum Size Mux Options

Single Port SRAM

High Speed

576 Kbits

8, 16, 32

Single Port SRAM

High Density

1152 Kbits

8, 16, 32

Dual Port SRAM

High Density

320 Kbits

4, 8, 16

ARM SRAM Embedded Memory IP may be used in complex SoC designs that require many types of IP across the design. In addition to SRAM IP, ARM offers a wide variety of compatible Processor to Pads IP including ARM Processor, Multimedia, System and Physical IP, with which to develop your SoC.

Visit DesignStart to find ARM IP solutions for your SoC and start designing today.  

ARM Physical IP 

ARM Processor IP 

ARM System IP 

ARM Multimedia IP 

Register File Memory


Memory Controllers


Read Only Memory


System Controllers




Debug & Trace IP







You can view ARM SRAM and other Physical IP products in DesignStart. Registered users of DesignStart can download Front-End Packages for all products that enable a comprehensive IP evaluation including place and route. DesignStart also includes access to technical documentation, including Datasheets and Application Notes.

Start your design today with DesignStart! 

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