- High density and low power ROM memories suitable for BOOT code
- Broad support for all leading EDA vendors ensuring quick time to market Flexible business models like ‘free library program’ and ‘try before you buy’ allowing lowest cost of ownership
- Memory subcircuits optimized over multiple sub ranges to provide power, performance and area close to a custom design.
- Lowest risk solutions with ARM memories being used by IDMs, fabless start-ups, IC companies and design houses backed up by a knowledgeable customer support team available in multiple time zones
ROM
(View Larger ROM Image)ARM® Memory IP solutions include Diffusion and Via/Contact programmable ROMs suited for high density and low power applications. ROM compilers are available in over 15 different foundries and 65 process variants from 28 nm to 250 nm
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ROM (Read Only Memory) is for the permanent storage of data within an SoC or other integrated circuit application. ARM offers both Via Programmable ROM and Diffussion Programmable ROM delivering maximum flexibility in design application.
High Density memories are 30% smaller compared to High speed memories and designed for high array efficiency. Targeted for mainstream and cost sensitive applications, these memories and can achieve up to 7000Kbits/sq mm at 28nm technology.
Targeted for power sensitive handheld markets, these Low Power memories reduce leakage current by up to 30% over the standard memories. These memories are . Multiple power management modes available providing up to 20x reduction in leakage in power down mode over the regular standby mode
- Depending upon foundry, geometry and flavor the Register file compilers support multiple features to ensure optimal implementation of all types of designs
| Key Features | Benefits |
|---|---|
High density and low power architecture | Minimizes die area to reduce die and packaging cost |
Multiple power management modes with power gating and multi-voltage operation | Flexible power management allows packaging cost reduction, competitive product with higher battery life |
| Flexible margining features | Allows yield/performance tradeoff |
| Optional integrated pipeline | Allows high throughput |
| Soft Error repair | Enables yield optimization |
| Advanced test features | Enhances product quality and minimizes field returns |
| Pseudo Scan | 1. Cuts down test time drastically by orders of magnitude reducing overall product test cost significantly 2. Improved product quality lowers field failures |
- Power grid supported in all the advance nodes (90 nm and below). Multiple options for power rings supported in mature nodes.
- Metal 4 used as a top metal layer.
| 32nm ROM Compiler | |||
|---|---|---|---|
| Memory solution | Architecture | Maximum size | Mux |
| ViaROM | High Density | 1M bits | 8, 16, 32 |
| 40/45nm ROM Compiler | |||
|---|---|---|---|
| Memory solution | Architecture | Maximum size | Mux |
| ViaROM | High Density | 1M bits | 8, 16, 32 |
ARM ROM (Read Only Memory) Embedded Memory IP may be used in complex SoC designs that require many types of IP across the design. In addition to ROM IP, ARM offers a wide variety of compatible Processor to Pads IP including ARM Processor, Multimedia, System and Physical IP, with which to develop your SoC.
Visit DesignStart to find ARM IP solutions for your SoC and start designing today.
Visit DesignStart to find ARM IP solutions for your SoC and start designing today.
| ARM Physical IP | ARM Processor IP | ARM System IP | ARM Multimedia IP |
|---|---|---|---|
Mali-VE6 | |||
You can view ARM ROM and other Physical IP products can in DesignStart. Registered users of DesignStart can download Front-End Packages for all products that enable a comprehensive IP evaluation including place and route. DesignStart also includes access to technical documentation, including Datasheets and Application Notes.
Start your design today with DesignStart!
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