Register Files

Register Files Image (View Larger Register Files Image)
ARM provides Single Port, Two Port and Ultra High Density Two Port Register file compilers in variety of different architectures that support wide performance range for all types of SoC designs. Designers can choose from High density and High Speed Register files to optimize their design for speed, power and/or area. ARM® Register File memory compilers are available in over 15 different foundries and 65 process variants from 28nm to 250nm

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Used for the temporary storage of information, Register File Memory typically provides higher performance and better area utilization for smaller memory sizes than standard SRAM memory. Containing dedicated read / write ports and available in 1-Port and 2-Port versions ARM Register File memory IP typically finds usage in L1 cache solutions, temporary buffers or wherever smaller memory instances are required in an SoC design.
  • High Speed memories for speed critical designs and suitable for L1 cache applications 
  • High Density memories for mainstream and cost critical applications
  • Ultra High Density Two Port register file targeted for area/power critical SoCs
  • Broad support for all leading EDA vendors ensuring quick time to market
  • Flexible business models like ‘free library program’ and ‘try before you buy’ allowing lowest cost of ownership
  • Memory subcircuits optimized over multiple sub ranges to provide power, performance and area close to a custom design.
  • Lowest risk solutions with ARM memories being used by IDMs, fabless start-ups, IC companies and design houses backed up by a knowledgeable customer support team available in multiple time zones

  • Several choices of High Speed and High Density register files are available based on bank size, bitcell choice, Vt implant and low voltage operation.
  • High Speed memories are used for speed critical designs that can range up to multiple GHz range. High Speed memories are 30% faster than High Density memories.

    High Speed versus  High Density Memory Performance Bar Chart

  • Targeted for maistream and cost sensitive applications, High Density memories are 20% smaller compared to High Speed memories and designed for high array effeciency. 

    High Speed vs High Density Memory Area


  • Ultra High Density Two Port register file provides 50% smaller area.
  • Targeted for power sensitive handheld devices, Low Power memories provides up to 30% lower leakage current.
  • Multiple power managment modes available providing upto 20X reduction in leakage in power down mode.

    Relativer Power Savings Bar Graph

  • Depending upon foundry, geometry and flavor the Register file compilers support multiple features to ensure optimal implementation of all types of designs  

Key Features 

High-performance architecture with flexibility to tradeoff density/performance Minimizes die area and reduce die cost
Multiple power management modes with power gating and multi-voltage operation Flexible power management allows packaging cost reduction, competitive product with higher battery life
Comprehensive redundancy scheme  Enables yield optimization
Flexible margining features Allows yield/performance tradeoff
Optional integrated pipeline Allows high throughput
Soft error repair Enables yield optimization
Advanced test features

Enhances product quality and minimizes field returns

Pseudo scan

1. Cuts down test time drastically by orders of magnitude reducing overall product test cost significantly

2. Improved product quality lowers field failures

  • Power grid supported in all the advance nodes (90nm and below). Mutliple options for power rings supported in mature nodes.
  • Metal 4 used as a top metal layer.
  • Flexible write mask options for partitioning bits.

 32nm Register file Memory Compilers 
Memory Solution  Architecture Maximum Size Mux Options
Single Port RF  High Speed  32K bits  4, 8, 16, 32 
Single Port RF  High Density  288K bits  2, 4, 8, 16, 32  
High Density Two Port RF    High Density     80K bits              1, 2, 4 
Ultra High Density RF  High Density  32K bits  2, 4 

 40/45nm Register file Memory Compilers 
Memory Solution   Architecture Maximum Size  Mux Options 
Single Port RF                   High Speed      32K bits              2, 4, 8              
Single Port RF  High Density   144K bits 2, 4, 8 
Two Port RF  High Density   72K bits  1, 2, 4 

ARM Register File Embedded Memory IP may be used in complex SoC designs that require many types of IP across the design. In addition to Register File IP, ARM offers a wide variety of compatible Processor to Pads IP including ARM Processor, Multimedia, System and Physical IP, with which to develop your SoC.


Visit DesignStart to find ARM IP solutions for your SoC and start designing today.

ARM Physical IP  ARM Processor IP  ARM System IP  ARM Multimedia IP 
SRAM Memory Cortex-A9 Peripherals Mali-400 
Read Only Memory Cortex-A5 Memory Controllers Mali-200 
Logic Cortex-R4 System Controllers Mali-VE6 
Interface Cortex-M3 Debug & Trace Mali-VE3 

You can view ARM Register Files and other Physical IP products in DesignStart. Registered users of Design Start can download Front-End Packages for all products that enable a comprehensive IP evaluation including place and route. DesignStart also includes access to technical documentation, including Datasheets and Application Notes.

Start your design today with DesignStart! 

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