| The RealView® Interface Tile 1 can be stacked with other Versatile products to create custom applications. The prototyping grid allows signals from Logic Tiles to be monitored and connected to additional components. There are a range of 0.1” pitch box headers which allow connection of on-board transceivers to external boards or equipment through ribbon cables. | 
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The tile connectors are tall so that ribbon cables can be attached even when the Interface Tile
is in the middle of a stack of boards. The Interface Tile allows fast application development, there is no need to wait for a board to be
made just to connect up to custom equipment or interfaces that are not present on the baseboard.
Features of the Interface Tile 1 The Interface Tile provides buffers and connectors that can be used with peripherals implemented in the FPGA of a Logic Tile. The following devices and connectors are present on the Interface Tile. Eight-channel 12-bit ADC operating at up to 200kHz Four-channel 12-bit DAC operating at up to 125kHz Two CAN bus drivers USB 2.0 host and on-the-go (OTG) transceivers Two I2C interfaces CMOS Camera interface Two stepper-motor interfaces An RS232 transceiver A Parallel ATA (IDE) disk drive interface Clock buffers to maintain good signal integrity 513-pin prototyping area with 272 I/O pins Eight general purpose DIL switches Eight general purpose LEDs Switches to disconnect unwanted transceivers
Note: The ADC, DAC, CAN bus, USB, I2C, camera, steppermotor, UART and IDE controller hardware is not part of the design of the Interface Tile. Any such logic must be implemented in an attached Logic Tile.
The Interface Tile can be mounted on top of a stack of boards including a baseboard, two Logic Tiles and an Analyzer Tile. The Logic Tiles contain the peripheral designs and the Analyzer Tile allows signals between adjacent tiles to be monitored.
It is possible to connect directly to an adjacent PCB (satellite board) in the same plane as the Interface Tile without the need for cables. It is also possible to extend the configuration JTAG chain through programmable logic components (e.g. PLDs) mounted on the prototype grid or a satellite board.
Devices mounted on the prototyping grid or satellite board can be connected to the global system clock and other clocks sourced by the Logic Tile above and below the Interface Tile in a stack. Such devices can also drive clocks and signals to the Logic Tile above and below the Interface Tile in a stack. | 
