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Interface Module IM-LT3ask ARM*
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The IM-LT3 Interface Module provides an interface between the high density Versatile connectors and the IntegratorTM family connectors.

IM-LT3 allows you to stack Core Tiles and Logic Tiles on top of Integrator boards like Core Modules and the CP baseboard. The IM-LT3 FPGA can be used to implement interface logic between the two boards.

Integrator IM-LT2 3Q Image

Front                Back

The Interface Module IM-LT3 is normally used to connect a Core Tile on top of an Integrator/CP baseboard. In this configuration the IM-LT3 implements the memory controllers and PrimeCell IP blocks for the peripherals on the baseboard. As a result, the Core Tile and the IM-LT3 together behave as an Integrator Core Module with a larger Virtex-II FPGA.

Thanks to its flexibility, IM-LT3 can be used in other configurations like the following:
  • As a motherboard for a Core Tile the IM-LT3 provides power, a JTAG connector and a basic memory system
  • As an interface between an ARM processor synthesized in Logic Tiles and an Integrator/CP baseboard

Interface Module IM-LT3 Key Features

  • Versatile and Integrator stacking connectors
  • Xilinx Virtex-II XC2V2000 FPGA
  • 2MB of ZBT SSRAM and up to 256MB of SDRAM in SDRAM DIMM
  • Four programmable clock generators
  • Connectors for power supply to Core Tiles or Logic Tiles for stand-alone operation
  • 20-way box header for connection of JTAG run control units, such as RealView Multi-ICE and RealView ICE
  • Trace connectors to allow tracing of ARM CPU cores synthesized in Logic Tiles

 

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RELATED PRODUCTS
   
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 Core Tile for ARM7TDMI >> 
   
 Core Tile for ARM926EJ-S >> 
   
 Core Tile for ARM1136JF-S >> 
   
 Core Tile for ARM1156T2F-S >> 
   
 Logic Tiles for Xilinx Virtex-II FPGAs >> 
   

Related
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Datasheet (1.2M .pdf)

RealView Hardware Platforms Flyer (588KB .pdf)

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Related FAQs
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*What is the clock architecture of the CP + IM-LT3 + CT7TMDI system?

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