15 August 2007

Enabling Communications Centric Design

New ways to integrate 50 million or more transistors

The intensifying demand for richer software applications continues to pull portable consumer devices ever closer to their tethered relatives. Such market driven requirements push the performance, power, and integration targets that must be delivered by silicon hardware. Multimedia-enabled mobile handsets provide a good example of this consumer driven complexity, today. Manipulation of graphics and video data requires an approach that can handle much higher bandwidths than designs that process voice alone. And to satisfy increasing demand for sophisticated functionality – email, GPS, web browsing, high-resolution cameras, etc. – designers have to find cost-effective ways to implement very large chips that now employ multiple systems.

This is becoming a design trend. Every advance to a new technology node allows designers to integrate more and more transistors on a single chip with higher clock speeds. Sub-systems that previously existed as separate chips are now integrated into a single device enabling reductions in package count, pin count, power consumption and cost. What was traditionally known as system on chip (SoC) design is now fast becoming just a sub-set of the functionality in today’s Super SoCs.

Implementation of such complex Super SoCs demands common resources to be shared between increasing numbers of independent functional sub-systems. The challenge to the system designer is how to efficiently manage the rising complexity and magnitude of these data flows. Traditional approaches to systems design are ill equipped to deal with this growing traffic management problem.

Limitations of Traditional Approaches
i) External Memory
The one component every system can pretty much guarantee it needs is access to storage in the form of off-chip memory. With increasing sub-system integration the bottle neck to realising system performance becomes how to manage the traffic to and from memory. Traditionally this has been performed by a single component operating in relative isolation – the memory controller. With multiple functions on chip each possessing distinct data characteristics and requirements, the problem becomes one of system level traffic management.

However, while processing speed has increased at 40% per year (inline with Moore’s law), memory speed has increased at only 9% annually. Despite innovations such as double data rate clocking (DDR Memory) and wider memory busses this divergence problem continues to worsen, exacerbated by further functionality integration inside the SoC.

ii) Internal Memory and Caching Architectures
Traditionally, system designers have sought to ease the data traffic to external memory using intermediate or local storage to reduce the stress at the off chip interface. Commonly used technologies include cache memory for processors, FIFO buffers for real-time functions, and increasing use of small on-chip memories. Effective use of such technologies depends on reliably predicting the interaction between data and memory. In an ever more complex SoC, this becomes impossible by pure paper and pencil methods.

iii) Bus Interconnect Fabric
Early SoC architectures typically witnessed a handful of primary processing elements (masters), peripheral functions (USB, Firewire, etc.), and off chip memory, connected together using a single shared bus. Such schemes were well matched to the low system bandwidth requirements.  However increasing SoC capabilities and performance create new requirements around how to handle complex and demanding intra chip traffic.

More recent concurrent bus architectures such as multi-layer bus structures add dedicated bandwidth to support each new block of functionality (bus master) via a crossbar switch configuration. Multi-layer interconnect provides an excellent solution for bandwidth intensive systems, but requires significant trade-off against cost and complexity as the number of bus masters grows.

As next generation microchips become a platform of independent sub-systems, the design of efficient interconnect requires a proper understanding of the system-level communication requirements and how other parts of the traffic management solution interact to produce an optimized result. In itself interconnect is just one part of the solution.

Changing Complexities in SoC Design
To properly support the levels of integration demanded today, design teams need a new communication-centric approach to chip design. Understanding system traffic profiles and performance requirements help to guide architectural decisions very early in the design process. This information helps the system designer to make decisions about how to efficiently partition the design and support each sub-system with appropriate traffic infrastructure.

Efficient Communication-Centric Design
To enable efficient communication-centric design, as well as IP for processing data, design teams will need to use more traffic management IP such as complex interconnect, memory controllers, direct memory access (DMA) controllers, cache and interrupt controllers and many other ancillary functions. These solutions need to be weaved together to form a cohesive, optimised solution to system level traffic management. Furthermore, system designers will benefit from new tools in the design flow to help them thoroughly understand the traffic management issues within their system. This information will be critical in making decisions concerning the design partition.

Supporting the use of IP blocks in different design scenarios requires access to configurable IP that can come together to form this traffic management fabric. The IP solution must also include behavioural models to ensure excellent simulation speed so that designs can be analysed with a representative level of system activity.

System integration of the IP fabric must be automated, easy to use and allow rapid iteration. During the architectural investigation, system designers will need to adopt more accurate and flexible tools for performance evaluation. These should support monitoring and analysis for system metrics such as bandwidth, latency and efficiency.

ARM Fabric Solutions
ARM is developing new tools and IP around the AMBA® on-chip bus specification to respond to the growing need for communication-centric design. AMBA is the de facto specification for on-chip bus implementation that has wide support across the industry and its implementation is scalable for power, area and speed.

AMBA Designer is an analysis environment that supports system performance analysis and the instantiation of optimized IP. AMBA Designer uses RealView® SoC Designer technology to provide a fully-featured easy-to-use toolset providing complete support for the latest configurable PrimeCell® IP from ARM.

The ARM PrimeCell library is enhanced for communication-centric design with the addition of enhanced interconnect and controller IP. This is a broad, configurable portfolio that provides the best support for ARM processors.

ARM views the continued development of fabric IP, including interconnect and analysis tools, as being fundamental in allowing system designers to get the best out of a rapidly growing pool of high-performance on-chip resources that come with higher levels of integration.