36 fully-independent SAS and SATA ports
SSP, SMP, STP and SATA Protocol support
SSP Target and Initiator
SMP Target and Initiator
STP Target and Initiator
Supports 1.5 and 3 Gb/s SAS and SATA data transfer rates
Port independent auto-negotiation
Ports are non-denominational
Initiator or Target connect
Provides a low latency connection router with crossbar module to efficiently create and maintain connections
Direct, Subtractive decode, and Table routing methodologies supported
Provides a scalable interface that supports up to 1024 SAS addresses
Supports wide and narrow port configurations
Allows re-use of routing table resources across all of the phys composing a wide port
Allows any number of phys for wide port support
Phy-based Zoning for system security
SATA/SAS HDD spin-up sequencing, configurable on a per-phy basis
SGPIO (SFF-8485) support provides additional data modulation for blink rates and blink patterns
8 GPIO pins
3 LEDs per phy
Link Status, Drive Activity, Fault LEDs outputs
Can be used as GPIOs
Integrated ARM Processor
SEP functionality
Drive management
Extended SAS SMP functions
Internal 8KB ROM can be used for boot-options
External interface support
Flash or SRAM memory
Flash for boot option
SRAM for overflow ARM processor code
EEPROM interface for nonvolatile storage of hardware configuration
External EEPROM not needed if internal ROM is used for boot options
Three I2C interfaces
One I2C interface dedicated to communication with external SEP
Two I2C interfaces for connecting external sensors
UART support for serial debugging
Supports JTAG testing
Diagnostic capability
Manufacturing utilities
Integration utilities
Individual phy power management
672 FPBGA package, 27 x 27 mm, 0.13um Gflx process technology
Software Development Kit
Common programming model for internal and external processor support
API with sample code to implement enclosure management
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