CoreLink DMC-520 Dynamic Memory Controller
Optimised and efficient access to the DRAM is critical to the performance of any Enterprise SoC. As the number of processing elements on a chip increases so the demand for data increases. As the DRAM technology has evolved to DDR4, the frequency of operation rises, but also the complexity of making best use of the DRAM increases. Managing the differing demands of multiple processing elements while trying to make optimum use of DRAM is the challenge faced by a Dynamic Memory Controller.
DMC-520 is ARM's 5th generation of Memory Controller. DMC-520 has been designed to meet the needs of an Enterprise system based around a Cache Coherent Network product from ARM. DMC-520 is a key part of ARM's End-to-End Quality of Service (QoS) scheme which includes features distributed across both Interconnect and Memory Controllers.
DMC-520 has an advanced QoS based scheduling and arbitration algorithm. QoS values defined by the system are used to re-order transations to be sent to memory. The DMC arbitration uses bank and row status to aggressively re-order transactions to optimise both bank parallelism and in row hits.
DMC-520 has been specified, designed and validated in conjunction with ARM's CoreLink 500 System IP.
