CoreLink System Memory Management Unit

CoreLink MMU-400 Performance Specification

Typical TLB hit access latency 23 cycles, miss latency depends on memory sub-system infrastructure .

CoreLink MMU-500 System Memory Management Unit

ARMv8 translation table format

• 4kB / 64kB granules @ stage 1 / 2
• DVMs enhanced
• Invalidation by IPA
• XO permission

Larger input address

• 32 bit VA or 64 bit VA (49 bits)
• Up to 48 bit IPA (stage 2 only)

Larger output address range

• Up to 48 bit IPA (stage 1 only)
• Up to 48 bit PA (stage 2)

Distributed TLBs

• Point to point connection
• To increase TLB efficiency and to save power and area
• Uses n x 1:1 TLB-TCU interface

CoreLink MMU-400 System Memory Management Unit

The MMU-400 provides:

•         Translation of intermediate-physical-address (IPA) to physical-address (PA) – stage 2 translation

•         Multiple transaction contexts that apply to specific streams of transactions

•         Fault handling, logging, and signalling

•         Debug and performance monitoring

The diagram below shows a single MMU-400 in an example Cortex-A15 and CoreLink 400 system. In this case it is performing address translation functions for a CoreLink DMA-330 DMA Controller.