• Clean decode table based on 5-bit register specifiers
• Instruction semantics broadly the same as in AArch32
• 31 general purpose 64-bit registers accessible at all times
• No modal banking of GP registers - Improved performance and energy
• Program counter (PC) and Stack pointer (SP) not general purpose registers
• Dedicated zero register available for most instructions

Key differences from A32 are:

• New instructions to support 64-bit operands. Most instructions can have 32-bit or 64-bit arguments
• Addresses assumed to be 64-bits in size. LP64 and LLP64 are the primary data models targeted
• Far fewer conditional instructions than in AArch32 conditional {branches, compares, selects}
• No arbitrary length load/store multiple instructions LD/ST ‘P’ for handling pairs of registers added A64

Advanced SIMD and scalar floating-point support are semantically similar to the A32 support; they share a floating-point/vector register file, V0 to V31. A64 provides three major functional enhancements:

• More 128 bit registers: 32 x 128 bit wide registers; can be viewed as 64-bit wide registers
• Advanced SIMD supports DP floating-point execution
• Advanced SIMD supports full IEEE 754 execution; rounding-modes, Denorms, NaN handling

There are some additional floating-point instructions for IEEE754-2008:

• MaxNum/MinNum instructions
• Float to Integer conversions with RoundTiesAway

The register packing model in A64 is also different from A32:

• All vector registers 128-bits wide, Vx[127:0] :
  • Double precision scalar floating point uses Vx[63:0]
  • Single precision scalar floating point uses Vx[31:0]