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ARM And Synopsys Announce Availability Of Reference Methodology For All Synthesizable ARM Cores

03 March 2003

Streamlined Process Speeds Deployment Time and Increases Quality of ARM Core Implementation

CAMBRIDGE, UK AND MOUNTAIN VIEW, CA. – March 3, 2003 – ARM [(LSE:ARM); (Nasdaq:ARMHY)], the industry's leading provider of 16/32-bit embedded RISC processor solutions, and Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) design software, today announced the availability of the ARM-Synopsys Reference Methodology as an integral part of all ARM® synthesizable cores. The ARM-Synopsys Reference Methodology significantly streamlines the process used by ARM Partners to port synthesizable ARM microprocessor cores to their chosen technologies, by reducing the time required to harden and model the core from months to weeks.

The new ™ core family, announced at the end of 2002, was the first synthesizable ARM core to be released with the ARM-Synopsys Reference Methodology fully integrated into the product. All ARM synthesizable core families-- the™ family, the™ family, the ™ family and the ARM11 family -- have now been upgraded to include the ARM-Synopsys Reference Methodology as an integral part of the product.

"Providing a superior reference design flow is strategic to our business," said Simon Segars, excective vice president, engineering at ARM. "When we enable ARM partners to do their own physical implementation starting from synthesizable ARM cores, we must provide proven methods for retaining compliance with our architecture in their implementation process. Our ongoing collaboration with Synopsys is enabling us to maintain our target of ARM core use being as easy as deploying a compiled RAM cell, thereby giving our partners a significant market advantage."

The ARM-Synopsys Reference Methodology provides an efficient, proven route from the register transfer level (RTL) to GDSII, creating a core that is compliant with the ARM architecture, and which has the necessary models required to deploy it as a reusable component. This "application specific" hardening enables ARM partners to benefit from the flexibility of a soft core while maintaining the predictability, performance and ease of deployment of a hard core.

"The ARM-Synopsys Reference Methodology takes full advantage of Synopsys' complete RTL-to-GDSII tool flow including, the new SoC test automation solution in Synopsys' DFT Compiler SoCBIST," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "The key components of the ARM-Synopsys Reference Methodology -- Design Compiler, Physical Compiler, Astro, and PrimeTime -- are also the anchors of our recently announced Galaxy™ Design Platform. We will continue working with mutual customers to accelerate their deployment of ARM's synthesizable cores."

Availability
The ARM-Synopsys Reference Methodology is available now from ARM, as an integral part of the latest release of each synthesizable core and supports the following Synopsys tools: Floorplan Compiler, HDL Compiler™, DFT Compiler™ SoCBIST, Physical Compiler®, DC Ultra™, Power Compiler™, Design Compiler®, PrimeTime®, DesignWare®, TetraMAX®, Formality®, VCS™ and Astro™. The Reference Methodology is modular and based on standard interfaces allowing for the integration of complementary tools.

About ARM
ARM is the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions. The company licenses its high-performance, low-cost, power-efficient RISC processors, peripherals and system-on-chip (SoC) designs to leading international electronics companies. ARM also provides comprehensive support required in developing a complete system. ARM's microprocessor cores are rapidly becoming a volume RISC standard in such markets as portable communications, hand-held computing, multimedia digital consumer and embedded solutions. More information on ARM is available at http://www.arm.com/

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and is located in more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/

ENDS

ARM is a registered trademark of ARM Limited. ARM7, ARM9E, ARK10E and ARM11 are trademarks of ARM Limited. "ARM" is used to represent ARM Holdings plc (LSE: ARM and Nasdaq: ARMHY); its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; and ARM Consulting (Shanghai) Co.Ltd.

Synopsys, Design Compiler, DesignWare, Formality, Physical Compiler, PrimeTime and TetraMAX are registered trademarks of Synopsys, Inc. Astro, Design Compiler, DCUltra, DFT Compiler, Galaxy, HDL Compiler, Power Compiler and VCS are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

Editorial Contacts:
Eileen Hunt
Synopsys, Inc.
650-584-5374
elhunt@synopsys.com  

Michelle Spencer
ARM Ltd.
+44 1628 427780
michelle.spencer@arm.com

Darren Ballegeer
Edelman Public Relations
(650) 429-2735
darren.ballegeer@edelman.com