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ARM The Architecture For The Digital World  

TSMC Open Innovation Platform forum (OIP)

Venue:

San Jose Convention Center

Location:

San Jose, CA

Date:

18 October 2011

Room/Booth/Stand:

IP Track Room & General Session Hall 1

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Join us at the TSMC Open Innovation Platform forum (OIP) and learn about ARM’s latest processor and Physical IP tuned for TSMC technologies. The forum features a one day-long conference combining morning keynotes and afternoon technical tracks. This forum is an “invitation only” event, please register here

ARM’s own Mike Inglis, EVP and General Manager of the Processor Division will detail how ARM’s strategic collaboration with TSMC is accelerating time to volume production of advanced SoC designs. ARM will also provide details on our hard macro solutions for advanced TSMC processes during the afternoon IP track.

The ARM booth will feature a variety of ARM products and a theater with short product overviews throughout the day.October 18th, 2011 (Tuesday) 8:00 a.m. – 6:30 p.m.San Jose Convention Center, CA Register Today.

We look forward to seeing you at our Booth # 311.

 

ARM Speaking

Topic: An Introduction to ARM’s Hard Macro Solutions for Advanced TSMC Processes

Speakers: Sumit Sahai & Dermot O'Driscoll

When: 10/18/2011 2:30 – 3:00

Where: IP Track Room

 

ARM Keynote:

Topic: Enabling Smart System Design Through Collaboration, Optimization and Scalability

Speaker: Mike Inglis - EVP and General Manager, Processor Division

When: 10/18/2011 10:00- 10:30am

Where: General Session Hall 1

Abstract: Growth in end-user devices is creating significant opportunities across all markets from mobile computing and home entertainment to the servers that provide content and connectivity. These opportunities bring challenges to SOC designers to increase integration, performance, and power efficiency.

Mike Inglis, EVP and GM of ARM Processor Division, will discuss these challenges and how ARM and TSMC are collaborating to enable smart system design through scalability, collaboration, integration and optimization.