Cadence Design Systems has further built on its relationship with ARM to roll out an optimised methodology kit, which the company claims will aide designers in enhancing performance, power utilisation and area for synthesizable ARM® processors.

Cadence said that the Optimization Methodology Kit for ARM Processors reflects its ongoing strategy of delivering higher level productivity, neatly tied to customer end-product goals. This was kicked off in the first quarter of this year with the launch of Cadence Virtuoso Wireless Flows. There is little doubt that the latest announcement will more tightly integrate the companies’ products, which must be a good thing for users.

Cadence has made no secret of its decision to go down the kit road. Ajay Malhotra, senior VP of marketing at Cadence said the market can expect more Cadence kits in the near future in areas of wireless, networking and consumer electronics as Cadence moves to a more focused kits approach.

Cadence said that each kit will focus on addressing today’s key design challenges and the ultimate Holy Grail, greatly reduced time-to-market. By simplifying the application of Cadence technology, customers can focus their design resources on the key to success – differentiation.

The Cadence Optimization Methodology Kit for ARM processors builds on the companies’ existing teaming on a number of areas, including IC design and power management and verification to provide enhanced solutions for application specific needs.

Cadence Kits take design challenges head-on by combining a verified methodology, packaged in platform flows, with IP and consulting all demonstrated on a representative reference design. As you would expect, the kit is optimized for Cadence tools, but there is nothing stopping users plugging in a third party tool.

The Cadence Optimization Methodology Kit for ARM Processors builds on a solid foundation, the ARM-Cadence Encounter Reference Methodology. The latest kit adds Cadence Encounter RTL Compiler synthesis, First Encounter silicon virtual prototyping, front-end views for the ARM Artisan® SAGE-X™ standard cell libraries for TSMC's 0.13 micron and 90 nanometer G processes to the mix.

Cadence and ARM are no strangers when it comes to working on deliverable solutions together. As two founding members of the Silicon Design Chain Initiative they’ve worked on a number of successful projects, aside from the ARM-Cadence Reference Methodology.  One example being accelerated SoC emulation integrating the Cadence Incisive functional verification platform with ARM’s Integrator™ Logic Tile family.

Today’s complex design processes scream out for collaboration.  By pooling resources, ARM and Cadence are underlining the necessity for simplification of EDA design technology to meet the consumer’s thirst for high performance technology that doesn’t guzzle power.  Design teams will welcome the development of the new Cadence Optimization Methodology Kit for ARM Processors, which has been the result of the continuing strong relationship between Cadence and ARM.