04 March 2009

ARM, Renesas & Synopsys Low Power Verification Manual

‘The Verification Methodology Manual for Low Power (VMM-LP)’ authored by ARM, Renesas Technology and Synopsys has been launched.

The VMM-LP book enables broad deployment of industry best practices to accelerate the verification of low power designs. Leveraging the collective verification and IP experience of more than 30 companies with real-world low power verification experience, the book builds on the methodology originally published in the proven ‘Verification Methodology Manual for SystemVerilog’ book developed by ARM and Synopsys.

Low power design techniques have become increasingly complex and have led to an leap in verification complexity, creating a need for a well-understood, robust, and reusable verification environment to achieve power goals and first-pass silicon success. The VMM-LP book documents the common causes of low power bugs, provides rules and guidelines for low power verification, specifies a SystemVerilog base class library facilitating the setup of a reusable verification environment, and recommends assertions and coverage techniques to accomplish comprehensive low power verification.

The methodology described in the VMM-LP book allows verification teams to attain coverage closure and pinpoint bugs using assertions. It can be implemented using voltage-aware static and dynamic verification tools, such as MVSIM with the VCS simulator and MVRC, which are part of the Eclypse low power solution from Synopsys. These tools are capable of checking low power designs for the rules documented in the VMM-LP book. The base classes will enable the infrastructure to create a structured and reusable verification environment based on the VMM-LP.

The lead authors of the VMM-LP book are Srikanth Jadcherla, group director of Research and Development at Synopsys, Janick Bergeron, Synopsys Fellow and moderator of the Verification Guild web site, Yoshio Inoue, chief engineer, Design Technology Division, Renesas Technology Corp and David Flynn, ARM fellow and co-author of the Low Power Methodology Manual (LPMM) [Springer].

The VMM-LP book is available today for purchase through the VMM Central web site (www.vmmcentral.org/vmmlp). Additionally, customers can download a PDF version of the book and register to receive notification about the availability of the source code for the VMM-LP SystemVerilog base classes from VMM Central.