25 October 2005

STMicroelectronics New SPEAr Member Has Advanced ARM Core

STMicroelectronics (STM) has confirmed it is sampling an ARM based SoC, dubbed SPEAr Head, a new addition to its SPEAr (Structured Processor Enhanced Architecure) family.

SPEAr Head integrates USB 2.0 host/device and 10/100 Ethernet interfaces, and targets embedded control applications such as digital engines for printers and scanners.

SPEAr Head integrates an advanced ARM926EJ-S core running at 266MHz, a complete set of IP (intellectual property) blocks and a configurable logic block that allows flexibility in high-complexity system implementation. The new device makes it possible to achieve extremely fast customisation of critical functions in a fraction of the time and cost required by a full-custom design approach, according to the company.

“ST continues to deliver SoCs that have a proven and tested architecture and offer state-of-the-art processor cores, technology and sophisticated IP, thereby minimizing customer investment and allowing them to leverage their core competences, which can be easily customized in the SPEAr family’s configurable logic element, as if it was a fully custom device. Specific IP, such as a dithered PLL, special I/Os to minimize on-board reflections, automatically reconfigurable DDR/SDRAM interface and a distributed DMA architecture make this chip unique in the market,” said Vittorio Peduto, General Manager of ST’s Computer Systems Division.

The new device includes: an ARM926EJ-S running at 266MHz with 32 Kbytes of Instruction cache, 16 Kbytes of Data cache, 8-Kbyte Data-TCM (Tightly Coupled Memory) and 8-Kbyte Instruction-TCM, and three USB2.0 ports (two hosts and one device supporting high speed mode); an Ethernet 10/100 MAC; a 16-channel 8-bit A/D converter; an I2C interface; three UARTs; SDRAM memory interfaces at 133MHz supporting DDR and SDR; SPI interface supporting serial FLASH/ROM; one full USB-dedicated PLL and one dithered system PLL; and 200-kgate (ASIC equivalent) of configurable logic connected to four banks of 4 KBytes SRAM each. A Real Time Clock, Watchdog and four general-purpose timers complete the SoC structure. Additionally, the device supports a wide range of operating systems, including Linux, Nucleus, uItron, and Vxworks.

Samples of SPEAr Head are already available. Full development boards will be shipped by December 2005.