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Latest blog posts
September 19, 2025
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Unlock the power of SVE and SME with SIMD Loops
September 18, 2025
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Reading time 16 minutes
Building an on-device multimodal assistant for automobiles
September 17, 2025
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Reading time 9 minutes
Out-of-band telemetry on Arm Neoverse based servers
September 16, 2025
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Reading time 9 minutes
Optimizing Code Cache Performance for Large Code Footprint Java Applications on Neoverse
Latest community activity
September 19, 2025
processus time double after fews seconde
hi,
my application use android java JNI to process camera vidéo in real time. The C part use openCL and multicore threading with médiatek 9200+ and mali G715.
Something strange append with the application. After fews seconde of processing...
hi,
I did some test this morning. And this time i removed all the multi core threading. And the big surprise is there is no more double time. So i conclude that it is the use of the CPU or multicore threading that cause the problem. All OpenCL command are fine, enqueuemapbuffer, enqueuewritebuffer and enqueuereadbuffer.
It look like the massive usage of the CPU is my problem. As soon as i start the massive CPU work the problem appends. But i do not anderstand why it slow done after alway the same amount of frame proceced.
Race Conditions in CXS interface protocol. Why?
According to the AMBA CXS specification, there is a section describe about the RACE conditions with below elaboration.
The Receiver asserts the CXSACTIVEACK signal, to move from ACTIVATE to RUN, and starts sending
credits:
— The Receiver is permitted to...
Ask a question in a forum.
Race Conditions in CXS interface protocol. Why?
According to the AMBA CXS specification, there is a section describe about the RACE conditions with below elaboration.
The Receiver asserts the CXSACTIVEACK signal, to move from ACTIVATE to RUN, and starts sending
credits:
— The Receiver is permitted to...
about 21 hours ago
Locking this thread, as it a duplication of community.arm.com/.../race-conditions-in-cxs-interface-protocol-why
timing diagram
Hi All,
Is there any CHI timing diagram ? I can not find it in the spec
Thanks
Tom
CPAKs: Cycle accurate simulator/emulator for a Cortex M4 processor based board
Dear ARM community,
I am a PhD student in France. My research involves the detailed architectural simulation of ARM Cortex-M4 processors, for which I require a cycle-accurate model.
I have attempted to locate the necessary tools through the following...
1 day ago
You may be interested in Arm IP Explorer:
https://www.arm.com/products/ip-explorer
Arm also offers a number of options to support academia, see:
https://www.arm.com/resources/education
Thank for your reply. I requested access. But I need to simulate for M4 processor in order to get the sequence of instructions, as well as the time taken by each instruction to execute, from the processor . will these help ?
i.MX 8M Plus EVK connection error with arm developemnt studio withj DT stream
purchased i.MX 8M Plus EVK , DSTREAM-ST and connecting with DS-5 debugger to EVK.after 59% showing failed to connect to any device on the tartget.
please guide us if any mistake in DSSTREAM Connection to the i.MX 8M Plus EVK, else any procedure to debug...
September 18, 2025
Ask a question in a forum.
application firmware failed to start after jump from bootloader
I'm using Keil scatter file to put my bootloader @0x08000000, application @0x08010000, boot_tag @0x0800FE00, my bootloader firmware works, it print out application sp and reset_handler before call jump_to_app(), those to values match with .map file, but...
about 23 hours ago
Please read our knowledgebase article: https://developer.arm.com/documentation/ka002218/latest/
There are more things to consider than just the SP and the start address of the application.
Building an on-device multimodal assistant for automobiles
In this blog post, learn how we are only starting to see what is possible when powerful, privacy-first AI runs directly in your car.Compatibility of PWAKEUP of APB completer with Q-channel compliant clock controller
Hi,
What is the recommended way of connecting PWAKEUP of an APB completer with the Q-channel interface signals of a clock controller to ensure correct functionality.
Regards,
Rishi
Can you help?
Race Conditions in CXS interface protocol. Why?
Not answered about 23 hours ago
timing diagram
Not answered 1 day ago
Compatibility of PWAKEUP of APB completer with Q-channel compliant clock controller
Not answered 2 days ago