Olympus-SoC™ by Mentor Graphics Corporation

Back End Design

Product Description

Olympus-SoC™ by Mentor Graphics Corporation

Product Description

The Olympus-SoC IC implementation solution is purpose-built to address the performance, capacity, time-to-market, and variability challenges at advanced nodes. With full support for low-power design styles, signoff-quality timing analysis and optimization, and DFM-aware routing, Olympus-SoC delivers the highest quality layouts with fast turnaround and rapid design closure.

To achieve high performance and fast turnaround time, the Olympus-SoC place and route system concurrently addresses multiple design metrics like timing, area and signal integrity, across multiple analysis engines with a direct costing algorithm. The Olympus-SoC platform offers many differentiated technologies, including a timing driven placer, OCV-driven clock tree synthesis (CTS), industry’s best multi-corner, multi-mode (MCMM) optimization and a unique macro placement engine.

The Olympus-SoC platform provides seamless concurrent optimization for both power and timing, covering all operating modes and process corners through all stages of the flow. It completely automates UPF based multi-voltage  design flows with automatic power grid routing for multiple voltage supplies, support for dynamic voltage and frequency scaling (DVFS) to handle varying supply voltages and clock frequencies, and auto placement and routing of special cells such as level shifters, isolation cells, and MTCMOS switches. Olympus-SoC also provides concurrent multi-Vt optimization, power gating, retention flop synthesis, support for gas station methodology, and power-aware buffering and sizing. It also provides automatic power-aware clock tree synthesis (CTS) with smart clock gate placement, slew shaping, register clumping and concurrent MCMM optimization, ensuring a balanced clock tree with the minimum number of clock buffers.

Olympus-SoC delivers concurrent optimization of timing, signal integrity, die size, leakage and dynamic power across all design and process corners throughout the design flow. It automatically analyzes manufacturing variability issues and drives optimizations throughout the implementation, starting with floor planning, and continuing through feasibility, placement, optimization, clock tree synthesis, and routing. The next-generation routing architecture incorporates variation-aware timing optimization and litho-modeling to address DFM and OPC effects early in the design cycle. Early DFM analysis allows Olympus-SoC to provide a high correlation with industry-standard timing and physical verification sign-off tools.

Olympus-SoC’s ultra-compact database provides the industry's highest capacity and smallest memory footprint, allowing it to handle 100 million+ gate designs. Along with ability to handle any size design flat or hierarchical, Olympus-SoC offers a unique pseudo-flat capability, which is helping our customers get much better area and density. The patented “virtual timing graph” architecture enables Olympus-SoC to handle any number of timing views of the design with minimal impact on runtimes and memory requirements. Patent-pending physical synthesis technology gives highly-optimized results for multi-million gate flat designs in a single overnight run. New advances in performance bottleneck detection and analytical optimization address the complex challenge of constraint validation for "dirty" design data, providing robust optimization in the presence of ill-formed constraints.

Sign-off quality timing, extraction, and delay calculation are native to the Olympus-SoC kernel. Fully-multithreaded analysis engines and the industry’s only fully-parallelized timing and optimization engine slash run times by efficiently using the latest platforms, providing a 7x speedup on an 8-CPU machine. The combination of these features allows Mentor customers to achieve design closure on large complex designs in a fraction of the time required for existing design flows. Olympus-SoC customers are experiencing 2-3X faster design closure times in addition to an additional 30% power savings versus traditional tools.

Product Features

• Unique native MCMM architecture provides seamless concurrent optimization for both power and timing, covering all operating modes and corners through all stages of the flow.
• Optimizes physical designs for design-for-manufacturing (DFM) issues, such as critical area analysis (CAA), litho hotspots and chemical-mechanical polishing (CMP), across multiple design contexts and multiple manufacturing process windows.
• Ability to handle designs with over 100 million gates in flat mode, or any number of design hierarchy levels.
• Fully-parallelized architecture scales efficiently on multicore and multi-CPU platforms.
• Multi-corner, multi-mode (MCMM) optimization delivers higher performance and low power.
• Fewer iterations and less manual analysis required to reach design closure.
• Delivers more robust designs that are less sensitive to manufacturing variability.
• Excellent scaling on multicore and multi-CPU computing platforms
• Comprehensive low power design capabilities—the Olympus-SoC low power platform comprehensively handles the requirements of low-power design, while ensuring optimization of the overall solution without excessive design iterations, enabling engineers to rapidly deliver fully-optimized, power-efficient designs:

• Seamless concurrent optimization for both power and timing, covering all operating modes and corners through all stages of the flow.
• Completely automated multi-voltage flow with automatic power grid routing for multiple voltage supplies, support for Dynamic Voltage and Frequency Scaling (DVFS), and automatic placing and routing of special cells such as level shifters, isolation cells, and MTCMOS switches.
• Concurrent Multi-Vt optimization, power gating, retention flop synthesis, gas station methodology, and power-aware buffering and sizing.
• Power aware clock tree synthesis (CTS) with smart clock gate placement, slew shaping, register clumping and concurrent MCMM optimization that ensures a balanced clock tree with the minimum number of clock buffers.
• Unified Power Format (UPF)-based Netlist-to-GDSII flow including support for power state definition tables.

Olympus-SoC™

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

Target Platform(s)

• Linux

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• VFP9-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• VFP10
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A5
• Cortex-A50
• Cortex-A53
• Cortex-A57
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-M4
• Cortex-R4
• Cortex-R5
• Cortex-R7
• SC000
• SC100
• SC200
• SC300
• ARMv4
• ARMv5
• ARMv6
• ARMv7
• ARMv8
• StrongARM
• XScale
• Mali55
• Mali-200+GP2
• Mali-400
• Mali-T604
• Other

System IP

• Debug
• Interconnect Fabric
• Level 2 Cache Controller
• Memory Controller

Physical IP

• DDR I/O (DDRI/II)
• General Purpose I/O (Inline / Staggered)
• Register File Memory Compilers
• Specialty I/O (HSTL, SSTL)
• SRAM Memory Compilers
• Standard Cell Libraries

Security Software

• TrustZone™ Technology

 Contact Us