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Calibre® YieldEnhancer by Mentor Graphics Corporation



Back End Design

Product Description

Calibre® YieldEnhancer by Mentor Graphics Corporation

Product Description

Calibre® YieldEnhancer offers an automated approach to layout enhancements that will improve yield. It addresses the issue of area with a core philosophy to take advantage of any white space. This method improves yield without sacrificing area. To balance performance, YieldEnhancer offers both a net-aware capability and back annotation to the design database. To determine the impact on yield, YieldEnhancer works with Calibre YieldAnalyzer to measure the impact of the layout modification.

To reduce those hot spots in a practical and efficient way, Calibre YieldEnhancer provides you with automated layout enhancements that include built-in functions optimized to maximize coverage and minimize run times. Calibre YieldEnhancer performs multi-layer operations that support multiple configurations that maximize the coverage and minimize jogs. Configurations include 1) single via additions, 2) replacement of a single via with two symmetrically placed vias, 3) edge modifications based on multi-layer checks, such as enclosure and extensions rules, and 4) single layer grow operations. Layout modifications remain DRC clean while taking advantage of as much white space as possible. To ensure you maintain design performance, Calibre YieldEnhancer also offers both a net-aware capability and back annotation to the design database.

“Smart” Automated Fill Algorithms

Fill solutions become more challenging with each smaller node because manufacturing processes and physical interactions become more sensitive to metal density variations. In addition, the performance of the chip becomes more sensitive to parasitic capacitance (which is increased by adding metal fill) and variations in interconnect resistance (due to CMP impact on metal thickness). Calibre YieldEnhancer’s SmartFill technology combines density analysis with the filling operation to minimize the number of fill shapes added. Additionally, it provides such advanced capabilities as multi-layer fill shapes, and support for non-rectangular fill shapes to optimize performance of the fill.

SmartFill is designed to take multiple types of constraints, including Calibre’s unique equation-based design rule specifications. This capability enables designers to analyze fill solutions using continuous, multi-dimensional functions in place of linear pass-fail conditions. This provides users with a transition from a density-based solution to a model-based approach, by enabling them to consider 1st order effects other than density. For the most specific and customized fill solution possible, SmartFill uses information obtained from Calibre CMPAnalyzer that is derived using algorithms based on thickness simulation data from a full CMP simulation.

All modifications are fully back-annotated to GDSII, OASIS®, LEF/DEF, OpenAccess™ and Milky Way™ design databases.

Product Features

  • Increases profitability with a system that automatically makes layout modification to improve the design's yield.
  • Executes and visualizes enhancements from within all the popular layout environments
  • Improves design flow by integrating with the leading design databases such as OpenAccess or Milkyway.
  • Provides a layout modification platform for early yield ramp.
  • Automatically modifies the layout to improve yield, including via doubling, via extensions, and enclosures, as well as growing polygons to a minimum size.
  • SmartFill technology combines density analysis with the filling operation to minimize the number of fill shapes added, and innovative compression techniques minimize GDSII file size.
  • Extends Calibre platform beyond DRC functionality to address DFM issues.
  • Fully integrated with the Calibre tool suite

Calibre® YieldEnhancer

Market Segment(s)

  • Embedded
  • Enterprise
  • Home
  • Mobile
  • Mobile Computing

Target Platform(s)

  • Linux

Physical IP

  • DDR I/O (DDRI/II)
  • General Purpose I/O (Inline / Staggered)
  • Register File Memory Compilers
  • Specialty I/O (HSTL, SSTL)
  • SRAM Memory Compilers
  • Standard Cell Libraries
 
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