Calibre® nmDRC by Mentor Graphics Corporation

Back End Design

Product Description

Calibre^® nmDRC by Mentor Graphics Corporation

Product Description

Total cycle time is on the rise due to more complex and larger designs, higher error counts and more verification iterations. Calibre® nmDRC responds to the need for reduced cycle time with revolutionary new capabilities that differentiate Calibre nmDRC substantially from traditional DRC tools.

Calibre® Pattern Matching replaces text-based design rule checks with a visual geometry that ensures a precise and accurate implementation of the design specification. Automated pattern capture and search integrated with existing design environments make the process easy to use, reducing rule deck size and verification time while improving product quality and performance.

Calibre nmDRC's new Equation-Based DRC (eqDRC) capability fills the void between traditional DRC and DFM process simulators, bringing user extensibility and fast runtimes to a whole host of new design and process interactions. Identifying and prioritizing design layout issues that affect yield are a big drag on turnaround time. Some issues are simply too complex to capture with traditional DRC measurements. Equation-based DRC enables precise and accurate characterizations of complex, multi-variable and 2D/3D interactions that have a direct impact on manufacturability. This allows you to make reliable design tradeoffs, and to quickly determine the best fix.

Calibre Automatic Waivers provides automated recognition and removal of waived design rule violations in external intellectual property (IP), eliminating redundant error debugging while ensuring that all waived errors are properly identified during full-chip verification. Because Calibre Auto-Waiver is fully qualified by the foundry as part of Calibre nmDRC, you can be confident that no matter what process you are using, Calibre Auto-Waiver will accurately process all IP waiver information, saving you critical verification time and resources.

Integrated design for manufacturing (DFM) analysis and enhancement enable layout tradeoffs to minimize random, systematic and parametric yield loss. Simultaneous DRC, yield analysis and layout modification decrease the total time required to produce a layout that is not only design rule compliant, but also high yielding.

Direct database access enables designers to easily use Calibre nmDRC throughout the flow, regardless of their choice of design creation environment. Direct read of popular design and encapsulation databases (LEF/DEF, MilkyWay, OpenAccess, GDSII and OASIS®) speeds DRC cycle time by eliminating the need for a separate data streamout process step. Direct write enables back-annotation of DFM enhancements into design databases. Finally, support of the OASIS® stream file format reduces file size resulting in fast streamout and facilitating file transfer and data storage.

Product Features

• Fast turnaround: Hyperscaling provides fast DRC run time and high CPU scalability
• Advanced checking: Equation-based DRC enables advanced checking without complex rule decks for reduced area and improved tolerance to manufacturing variability

• Parallel debugging: Speeds identification, analysis and correction of violations by enabling a concurrent work flow
• Faster time-to-yield: Model-based verification, analysis, and visualization guide you to the errors that truly impact yield
• Investment protection: Straight drop-in to existing DRC flows. Leveraging over 3.5 million lines of SVRF code from 250nm to 45nm process nodes protects your investment in flow infrastructure, training, and rule decks

Calibre® nmDRC

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

Target Platform(s)

• Linux

Physical IP

• DDR I/O (DDRI/II)
• General Purpose I/O (Inline / Staggered)
• Register File Memory Compilers
• Specialty I/O (HSTL, SSTL)
• SRAM Memory Compilers
• Standard Cell Libraries

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