TimingExplorer by ICScape Inc.

Back End Design

Product Description

TimingExplorer is a physically-aware, multi-corner, multi-mode timing ECO tool for rapidly achieving timing closure in nanometer-scale IC designs. 

Physically-aware capability allows TimingExplorer to account for effects such as congestion and routing topology while making ECO, and the ability to directly read the timing graph from STA tools avoids differences introduce with re-calculating timing. The result is a great speed-up in processing and an acceleration in timing convergence. 

Designed to augment existing tools and flows, TimingExplorer has been used in production for over 6 years. It gives the fastest convergence of any tool available, and produces very high-quality layouts. 

Key Benefits:

• Reduces number of iterations through ECO cycle
• Reduces time through each iteration
• Achieves sign-off time correlation and layout correlation

 

Key Features:

• Fix hold, setup, max transistion and max cap violations
• Fix timing violations with clock ECO
• Timing-driven leakage power reduction
• Ultra-high capacity & speed
• Support hierarchical ECO capability
• Handles Multi-Corner-Multi-Mode timing violations
• Efficient buffer insertion
• Reduced congestion & power consumption

It is used by customers like ARM Partners on designs containing all types of ARM IP.  

TimingExplorer

Market Segment(s)

• Enterprise
• Mobile
• Mobile Computing

Target Platform(s)

• Linux

ARM Processor(s)

• Cortex-A53
• Cortex-A57
• ARMv8

Physical IP

• Standard Cell Libraries

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