ConMan by Excellicon

Back End Design

Product Description

ConMan is the first commercially available constraints compiler tool that automatically generates SDC for any level of hierarchy and for any mode of a SoC, thereby significantly shortening the timing closure cycle. ConMan provides an intuitive means of automatically compiling, verifying and managing sign-off quality correct-by-construction timing constraints.

ConMan also redefines the timing constraints landscape by aligning front-end to back-end early in the design cycle, thus eliminating the existing disconnect between timing assumed in simulation test benches, and the timing coded in the SDC files for implementation activities.

ConMan generates and maintains a single source of data for use by both front-end and back-end designers to capture, generate, verify and manage design timing constraints for all modes of operation while providing feedback to designer at all stages of the design. Using ConMan designers can start generating timing constraints right from the start of RTL development by front-end engineers all the way to the implementation stage by back-end team. As more information becomes available, user can take advantage of available data to further refine and complete the constraints. All information is traced through ConMan and can be reviewed through reports or visualization of simulated timing data.

Designer can manually feed timing information or optionally feed them from legacy SDC's and/or through simulation results for any block of the design hierarchy. ConMan automatically verifies all input data using its powerful formal symbolic simulation engine and then assembles & propagates all timing data throughout the design hierarchy, resolves conflicts, and presents data to designer for further refinement, if needed.

ConMan is intended to be used from early stages of the ASIC design cycle to the final timing sign-off:

ConMan

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

Target Platform(s)

• Linux

Physical IP

• DDR I/O (DDRI/II)
• General Purpose I/O (Inline / Staggered)
• Register File Memory Compilers
• Specialty I/O (HSTL, SSTL)
• SRAM Memory Compilers
• Standard Cell Libraries

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