Cadence Interconnect Workbench by Cadence Design Systems

ESL Tools

Product Description

 

CADENCE INTERCONNECT WORKBENCH

A cycle-accurate and automated performance analysis and functional verification solution for ARM® CoreLink™ interconnect System IP

The Cadence® Interconnect Workbench enables pre-tapeout SoC performance analysis and debugging, and reduces testbench development time by automatically generating the UVM testbench code.

The Interconnect Workbench is an interconnect performance analysis and functional verification solution for ARM® System IP. It combines automated generation of testbenches with a powerful interactive performance analysis and debug, enabling early optimization of the design and evaluation of its behavior under crucial mainstream and corner case traffic conditions. With its fully integrated automation and debug flow, engineers can avoid costly performance bugs discovered late in the project and reduce testbench development from months to hours.

Features/Benefits

·         Supports ARM® CoreLink™ System IP including CCI-400™, NIC-400™, and NIC-301™ and cascades of those IP

·         Shaping of interface traffic with VIP sequences to assess the system performance under various traffic load use cases

·         Supports performance sensitivity analysis to compare various implementation options and QoS configurations

·         Performance GUI to visualize, discover, and debug system performance behaviors

·         Automatically generated performance and verification testbench UVM code from AMBA Designer® IP-XACT

·         Automatically generated test suite to exercise legal combinations of masters and slaves

 

Cadence Interconnect Workbench

Market Segment(s)

• Enterprise
• Home
• Mobile

ARM Processor(s)

• Cortex-A15
• Cortex-A50
• Cortex-A53
• Cortex-A57
• Cortex-A7
• Cortex-A9
• ARMv7
• ARMv8

System IP

• Debug
• Interconnect Fabric
• Memory Controller

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