
The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus. The DB-I2C-MS-APB Controller IP Core can also interface a set of Registers within an ASIC / ASSP / FPGA device as well as interface Memory (e.g. SDRAM / SRAM / FLASH) to an I2C Bus.
The DB-I2C-MS-APB Controller IP Core, with its Finite State Machine & FIFO, targets embedded processor applications with high performance algorithm or I2C off-load from the processor requirements.
I2C Master / Slave Controller IP Core, Parameterized FIFO, APB Bus