Riviera-Pro by Aldec

RTL (Front End) Tools

Product Description

 

Aldec, Inc. product portfolio addresses verification needs of engineers crafting tomorrow’s cutting-edge SoC and FPGA devices. Aldec drives productivity and innovation by addressing a wide area of verification requirements -- starting from block, to chip, to system level. Aldec's Riviera-PRO is the industry-leading comprehensive design and verification platform which enables the ultimate verification environment (Testbench) productivity, reusability, and automation.

Riviera-PRO combines the high-performance multi-language simulation engine and advanced debugging capabilities at different levels of abstraction (TLM, RTL, and Gate-Level), and supports the latest Language Standards (VHDL 2008, SystemVerilog 2009, SystemC 2.3), TLM-driven embedded processor verification flows (C/C++, SystemC), virtual platforms technology (OVP), and industry standard Verification Libraries (OVM, UVM, VMM).

Feature Highlights:

• Advanced Verification Platform (UVM/OVM, VMM)
• Different Levels of Abstraction (ESL/TLM, RTL, Gate-Level)
• High-Performance Simulator for Mixed Language Designs
• IEEE VHDL, Verilog®, SystemVerilog, SystemC/C/C++
• Transaction-Level Debugging Environment
• Assertion-Based Verification (SVA, PSL and OVA)
• Code and Functional Coverage
• DSP Co-Simulation with MATLAB® and Simulink®
• Linux and Windows® 7/2008/Vista/XP/2003 32/64 Bit Support

 

Riviera-Pro

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

Target Platform(s)

• Linux
• Other OS

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A5
• Cortex-A53
• Cortex-A57
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-M4
• Cortex-R4
• Cortex-R5
• Cortex-R7
• ARMv8

System IP

• Interconnect Fabric
• Level 2 Cache Controller
• Memory Controller

Physical IP

• DDR I/O (DDRI/II)
• General Purpose I/O (Inline / Staggered)
• Specialty I/O (HSTL, SSTL)
• Standard Cell Libraries

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