Questa Verification Platform by Mentor Graphics Corporation

Product Description

Functional verification has evolved from gate and RTL simulation into a broader collection of verification tools. The complexity of SoCs is demanding changes in functional verification, forcing the integration of multiple point tools into flexible, open flows that integrate a broad arsenal of verification solutions. SoC verification complexity is managed by decomposing the problem and using the best solution, such as CDC verification, formal verification or mixed-signal simulation. This places tremendous importance on the verification plan and the ability to collect metrics throughout the process and across all verification tasks to track progress against the plan, allocate and manage resources efficiently, and identify trends as the project progresses against schedule.
At the same time, complexity is forcing design and verification to move up in abstraction to the transaction and algorithmic level with automated or manual refinement into an RTL implementation.
Software has become a major component of SoC system functionality, creating new requirements for block-to-system verification reuse and the need for system verification and debug. While software testing of SoC integration and basic functionality as well as the verification of low level driver software can be accomplished in simulation, long, complex sequences that exercise system functionality demand acceleration with full debug visibility. No one wants to compromise product quality. However, time-to market pressures dominate SoC projects. To deliver quality within schedule requires improving the time to achieve coverage and quality goals. The platform is composed of several technologies, each powerful on its own. Applied together, along with a comprehensive database and best-in-class verification management tools, the technologies deliver a powerful answer to myriad verification problems.

Product Features:
Unified Simulation, Coverage and Debug technology, built on a best-in-class simulator. The Questa Advanced Simulator achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimization algorithms for SystemVerilog and VHDL, improving SystemVerilog and mixed VHDL/SystemVerilog RTL simulation performance by up to 10X. Questa also supports very fast time to next simulation and effective library management while maintaining high performance with unique capabilities to pre-optimize and define debug visibility on a block by block basis, enabling dramatic regression throughput improvements of up to 3X when running a large suite of tests.

Questa SoC Verification provides processor-based system-level verification, using software tests to verify RTL and hardware/ software integration. The technology comes with a host of advantages such as ensuring chip power management, loading and booting operating systems, and running software applications. It accelerates simulation, enables instant replay, and offers virtual emulation — all of which serve to trim debugging time.


Intelligent Testbench Automation automatically generates sequences and works at the block, subsystem and SoC levels. The technology avoids redundancy and can achieve target coverage more than 10X faster than is possible with constrained random testing. The technology can be applied either to yield much faster runs or to allow the user to run more tests in the same amount of time — or somewhere in between — under the user’s control.


Questa Verification IP provides a collection of reusable testbench building blocks that are protocol- and interface-compliant, and can be used to verify that the design implements protocols correctly. The IP, with native support for OVM and UVM, facilitates simulation, formal verification and emulation, and enables straightforward test plan tracking.


Questa CDC Verification identifies errors that have to do with clock domain crossings – signals (or groups of signals) that are generated in one clock domain and consumed in another. It does so with structural analysis and recognition of clock domains and synchronizers, and with generation of metastability models for reconvergence verification. The technology checks all potential failure modes and presents to the user familiar schematic and waveform displays.


Questa Formal Verification complements simulation. With autodetection of common errors, and support of SVA, PSL and OVL assertions, the technology provides exhaustive verification without testbenches. Its capacity and performance allow for everything from early debug before simulation tests to post-silicon debugging.


Questa Low Power Verification enables early (RTL) verification of active power management applied to a complex design, to ensure that the power management architecture and behavior are correct and that the design will operate correctly under active power management. Questa PASim simplifies the verification process through automated error detection, visualization of power management architecture and behavior, and coverage data collection for power states and state transitions. Based on industry-standard IEEE 1801-2009 UPF for specification of active power management, Questa PASim integrates well with other UPF-based tools to support multi-tool and multivendor design and verification flows.


Questa Verification Management offers a slew of features for analysis and optimization. These include the Unified Coverage Database, results and trend analysis, testplan tracking and run management. Questa Verification Management efficiently ties all coverage related tasks together and gives all parties — system architects, software engineers, designers and verification specialists — real-time visibility into the project. This visibility helps to hit market windows on schedule, manage risk and jump-start the debug process.

Questa ADMS verifies complex analog/mixed-signal designs. The technology integrates four high performance engines: Eldo for general purpose analog, ADiT for fast transistor-level, Eldo RF for modular steady state and Questa Sim for digital. Its combination of languages and algorithms allows for both top-down design and bottom-up verification.


UVM and OVM provide a “methodology platform” so you can build your verification environment to take advantage of Questa technologies targeted to your specific application. The UVM/OVM libraries provide the infrastructure that enables you to assemble configurable VIP components and environments that can be reused from block-to-system and from project-to-project. For stimulus generation, Questa’s Intelligent Testbench Automation can be seamlessly integrated into your UVM/ OVM environment. The modularity of UVM/OVM lets you reuse your transaction-level testbench using both the Questa and Veloce platforms, while also letting you gather coverage data that you can later analyze using Questa Verification Management. Questa’s unique UVM/OVM debug capabilities make it easy to debug your testbench alongside your design, too.


Verification Academy
The Verification Academy is organized into a collection of free online courses (modules) and resources, focusing on key aspects of advanced functional verification designed to mature an organization’s verification process. Module topics include Assertion-Based Verification, FPGA Verification, Clock-Domain-Crossing Verification, Intelligent Testbench Automation and many others. Each module consists of multiple sessions allowing the viewer to pick and choose topics of interest as well as revisit topics for future reference. The Verification Academy is the most complete UVM/OVM online resource collection. You’ll find everything you need to get up to speed on UVM and OVM, whether it’s downloading the kit(s) or participating in online or in-person training. The UVM/OVM modules provide a great overview of methodology concepts, introductory to advanced, with videos that walk through useful code examples. The UVM/ OVM Online Methodology Cookbook is an online textbook to show you in more detail how to use the various features of the methodologies to create reusable verification components and environments.

Questa Vanguard Program (QVP)
The Questa Vanguard Program (QVP) brings world-class product integrations and interoperability to enhance Questa verification options and build a strong and comprehensive SystemVerilog ecosystem. QVP extends Mentor Graphics breadth of design and verification technologies through partnership with other industry leading companies that provide verification related tools and methods, verification IP, conversion services, training and consulting.

Questa Verification Platform

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• VFP9-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• VFP10
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A5
• Cortex-A53
• Cortex-A57
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-M4
• Cortex-R4
• Cortex-R5
• Cortex-R7
• ARMv8
• StrongARM
• XScale
• Mali55
• Mali-200+GP2
• Mali-400
• Mali-T604

Physical IP

• DDR I/O (DDRI/II)
• General Purpose I/O (Inline / Staggered)
• Register File Memory Compilers
• Specialty I/O (HSTL, SSTL)
• SRAM Memory Compilers
• Standard Cell Libraries