HASH and HMAC Cores
The SafeXcel™ IP HMAC MD5/SHA-1/SHA-2 Accelerators implement the MD5 and Secure Hash Algorithms (SHA-1 and SHA-2), as specified in RFC 1321, FIPS 180-2 and FIPS 180-3, including HMAC support as specified in RFC 2104 and FIPS 198. The hash algorithms are, for example, used for creation and validation of digital signatures, data integrity checking, password verification, key confirmation in key establishment protocols, time stamping, public-key infrastructure, and message authentication codes implementations such as HMAC.
Semiconductor designers require ready-to-use hardware implementations of the Message Digest algorithm 5 (MD5) and the Secure Hash Algorithm (SHA) that are silicon-proven and reliable, yet flexible to accommodate a wide variety of design goals. Part of AuthenTec's award-winning IP product portfolio, the Company provides its SafeXcel IP MD5/SHA Accelerators to meet these requirements. Designed for fast integration, low gate count, and maximum performance, they address the unique needs of semiconductor manufacturers and provide a reliable and cost-effective IP solution that is easy to integrate into SoC designs.
Applications
The SafeXcel IP MD5/SHA Accelerators are typically deployed in semiconductors for next-generation applications such as secure data communications, secure electronic transactions, and secure data storage. The hash algorithms are, for example, used for creation and validation of digital signatures, data integrity checking, password verification, key confirmation in key establishment protocols, time stamping, public-key infrastructure, and message authentication codes implementations such as HMAC. HMAC functionality is an optional function of the MD5/SHA Accelerator IP cores.
Standards Compliance
The SafeXcel IP MD5/SHA Accelerators implement the MD5 algorithm, as specified in RFC 1321, and the Secure Hash Algorithms, as specified in FIPS (Federal Information Processing Standard) Publication 180-2. The accelerators include I/O registers, hash calculation cores, message padding logic, and data scheduling logic.
Configuration Flexibility
The SafeXcel IP MD5/SHA Accelerator is available in a wide range of configurations that enable use in different applications and achieving different design goals, such as performance (up to 6Gbps @ 500MHz), gate count, and target cost. Any combination of the individual hash algorithms is available as a separate configuration.
SafeXcel-IP-57: HASH Accelerators
The SafeXcel-IP-57 accelerates Secure HASH algorithms. The core is available in various performance and latency grades and available in several configurations offering SHA-1 only, MD5 only, SHA-1/MD5 combined, SHA-256 only, SHA-1/SHA-256 combined, SHA-512 only, SHA-256/SHA-512 combined, etc.
SafeXcel-IP-57-HMAC: HMAC Accelerators
The SafeXcel-IP-57-HMAC accelerates Secure HMAC and basic HASH algorithms. The core is available in various performance and latency grades and available in several configurations offering SHA-1 only, MD5 only, SHA-1/MD5 combined, SHA-256 only, SHA-1/SHA-256 combined, SHA-512 only, SHA-256/SHA-512 combined, etc.
Features
SafeXcel™ IP-57 HASH/HMAC Core Family