The Arasan ONFI 3.0 compliant NAND Flash Controller IP Core is a full featured, easy to use, synthesizable design that is easily integrated into any SoC or FPGA development. Designed to support both SLC and MLC flash memories, it is flexible in use and easy in implementation. The controller works with any suitable memory device up to 128 Gb from leading memory providers such as Micron, Samsung, Toshiba, Hynix, and others. The IP core includes a host of configuration options from page size to band selects. The controller offers Hamming Code (1bit error correction and 2bit error detection) and BCH (option for 4-, 8-, 12-, up to 64 bit error correction) error code correction (ECC) for optimized performance and reliability. Additional features include the capability to boot from flash. The IP core supports the Open NAND Flash Interface Working Group (ONFI) 3.0 standard and is backwards compatible. It uses differential signaling on the clock and data lines and clocks at any frequency up to 200 MHz.