CSI-2 Transmitter IP Core by Arasan Chip Systems, Inc.

Product Description

The Arasan CSI Transmitter IP is designed to provide MIPI CSI 1.01 compliant high speed serial connectivity for camera modules in mobile platforms. Serial connectivity to the mobile applications processor’s CSI receiver is implemented using 1 to 4 D-PHY lanes, depending on camera sensor resolutions and the resulting bandwidth needs. This IP connects to the D-PHY’s through the PPI interface.

Initial configuration of this IP and its associated Arasan D-PHY can be done through programmed IO over a microcontroller bus, however, other bus interfaces can be provided upon request.

Pixel data received from over the Camera Sensor Bus is required to be in a byte aligned CSI-2 packet format. This IP calculates and appends an ECC value to a short packet or to the header of a long packet. For the payload of a long packet carrying pixel data, this IP calculates its CRC value and appends to the packet as a footer. The packet is buffered in a FIFO and sent to one or more D-PHY’s depending on the lane distribution scheme set by the camera sensor.

CSI-2 Transmitter IP Core

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

Target Platform(s)

• Android
• Linux
• Windows Embedded CE
• Windows Mobile

Companion Processor(s)

• Communication
• Flash
• I/O
• Multimedia

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• VFP9-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• VFP10
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A5
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-M4
• Cortex-R4
• Cortex-R5
• Cortex-R7
• SC000
• SC100
• SC200
• SC300
• ARMv4
• ARMv5
• ARMv6
• ARMv7
• StrongARM
• XScale
• Mali55
• Mali-200+GP2
• Mali-400
• Mali-T604
• Other

System IP

• Interconnect Fabric