C2C™ Chip to Chip Link™ Inter-chip Connectivity IP by Arteris

Product Description

The purpose of inter-chip connectivity IP is to connect two different chips together to share computing resources, limit chip-to-chip latency, or maintain the highest possible chip-to-chip bandwidth. Inter-chip connectivity is also often described as chip-to-chip, die-to-die or C2C links.

C2C natively supports the ARM AMBA AXI protocol transaction interface for connectivity within any type of system-on-chip.

Arteris offers the C2C Chip to Chip Link product and is also a contributor to the MIPI Low Latency Interface (MIPI LLI) specification.

Learn more about interchip connectivity IP by reading, "Interchip Connectivity: HSIC, UniPro, HSI, C2C, LLI...oh my!"

Chip to Chip Link (C2C) and the ARM AXI Protocol

Chip to Chip Link (also known as C2C) offers the capability to connect two chips without a PHY, using only DDR pads.  “C2C” is a trademark of Texas Instruments, Inc., and is a product containing TI and Arteris technology.

C2C connects to an SoC through native 64-bit ARM AMBA AXI ports, allowing SoCs using the ARM AMBA AXI protocol to easily connect to any other chip that also has a C2C IP block.

C2C for Mobile Phones

C2C’s primary purpose is to connect a mobile phone applications processor to a mobile phone modem. The 100ns round-trip latency of the C2C connection is fast enough for the modem to share the application processor’s RAM and to maintain enough read throughput for cache refills.

This enables the phone manufacturer to remove the modem’s dedicated RAM chip from the phone’s bill of materials (BOM).

C2C Benefits

Using C2C saves a mobile phone vendor at least $2 from RAM cost savings alone. This savings is even larger when one includes the benefits of reduced board area / cost.

Chip-to-Chip Link (C2C) Advantages

BoM Cost Savings

~$1.50 256Mb LPDDR1
~$2.00 512Mb LPDDR2
(cost estimates for 2011)

PCB Area Savings

72 mm2 (8x9mm) for LPDDR1
115 mm2 (10x11.5mm) for LPDDR2

C2C can also be used in non-mobile applications where low latency and high bandwidth between chips is required, such as co-processing applications.

Chip-to-Chip Link (C2C) Features

C2C Latency: 100 ns round-trip

C2C Connectivity: DDR pads

Transmit Pads required: 16 or 8

Receive Pads required: 16 or 8

C2C™ Chip to Chip Link™ Inter-chip Connectivity IP

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A5
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-M4
• Cortex-R4
• Cortex-R5
• Cortex-R7
• ARMv4
• ARMv5
• ARMv6
• ARMv7
• StrongARM
• XScale

System IP

• Interconnect Fabric
• Memory Controller

Physical IP

• DDR I/O (DDRI/II)
• General Purpose I/O (Inline / Staggered)
• Specialty I/O (HSTL, SSTL)