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System and IP memory map related information, specifically generation of ARM CMSIS files, definitions of ARM IP such as INTC, TIMER, GPIO, DMAC etc, capture and specification of system interconnect components such as NIC- 301, interaction with AMBA designer, creation of IP-XACT files, for example complete Cortex M3 and M4 definitions, generation of SW APIs, documentation and verification views, generation of AMBA interfaces such as APB and AHB-Lite, together with associated memory mapped registers, local decode etc, potential to generate other ARM specific views such as real view debug configuration files.
Register & Memory-Map Management
Effective HW/SW integration is one of the biggest challenges facing System-on-Chip (SoC) development teams. Registers and memory-maps are at the heart of the HW/SW interface. Socrates Bitwise manages the entire register and memory-map infrastructure for an IP or system, improving inter-team communications, enhancing design quality and greatly reducing workload.
The Problem: Many of the bugs and schedule slips that plague SoC designs originate from miscommunication and inconsistencies surrounding the HW/SW interface. Specifying and managing the HW/SW interface information, while maintaining synchronization between functionally and geographically diverse teams, is an essential but time-consuming and error-prone task. In order to succeed, teams must be able to rely on a single source from which to draw their information.
Your Solution: Socrates Bitwise manages HW/SW register, memory-map and interface definitions for IPs, subsystems or SoCs. Bitwise provides a single-source specification for register and memory-map information from which all design, verification, software and integration teams auto-generate the views they require, thereby remaining perfectly synchronized at all times. Bitwise enhances inter-team communications, increases levels of flow automation and significantly reduces development schedules. Bitwise provides a comprehensive environment that supports architectural planning, IP import, IP creation, and view generation. The result is a complete solution for HW/SW interface management that eliminates an entire category of bugs from your systems.
Fast and efficient path to a standardized IP repository
Reduce development costs through automation of time-consuming, tedious and error-prone tasks
Elimination of bugs due to human error or misalignment between engineering teams
Customizable importers and generators to ensure non-disruptive deployment
Cost-effective commercial replacement for legacy in-house solutions
Efficient IP reuse and accelerated derivative development
Low/No risk migration to new flows and standards
Guaranteed quality of design views due to correct-by-construction methodology
Fully interoperable solutions supporting import of standard formats including IP-XACT, Excel, VHDL / Verilog
Customizable importers to support customer-specific or other legacy formats
Comprehensive suite of standard output generators for hardware, verification & software code and documentation
Supports customization of standard generators or creation of customer-specific generators using a variety of common languages including Freemarker, Python and Perl
Comprehensive data model supporting configurable IP and multiple operational modes, in addition to ports, interfaces, register groups & arrays, complex access types and memories
Data model extension via user-defined properties to support customer-specific data and constructs
Full set of data syntax and semantic rule checks with real-time markers in the GUI and simple identification of error source
Effective visualization of IP & system content and structure to aid design navigation
Eclipse-based product supporting both a powerful and intuitive GUI and command-line operation; runs on Windows or Linux platforms