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Trek™ is a new approach to functional verification for complex system-on-chip (SoC) designs. A unique model-based test generation tool, Trek supports your natural thought process in SoC design, helping you "mind map" how your SoC should work and what the test flow should be. It helps you create scenario models that display your verification search space in an intuitive graphical form. Trek is used to verify SoCs with any mix of VIP including third-party, re-used or newly-created models. For the first time, you have the power to quickly develop and reuse verification knowledge at all levels of the system-on-chip design hierarchy.
Using these models, Trek automatically generates suites of C-code tests that you compile to quickly, and thoroughly, stress your SoC design. Checking is built in during testing. Afterwards, use the same scenario model graph to immediately spot the gaps in your coverage, and generate tests to close them.
Stimulus, checks and coverage closure in one simple, elegant and powerful EDA tool: Trek.
Trek gives you more complete coverage closure than you ever thought possible - with a fraction of the time and effort you are expending on verification testing today.
· Start SoC testing even before RTL is complete.
· Automatically generate multiple tests and fully stress your design.
· Gain a deeper understanding of your SoC design as you build and refine scenario models using your knowledge of design specifications, verification plans, functional requirements and implementation - knowledge that can be leveraged in future generations of your product.
· Use easy-to-interpret flowchart-style graphs to share your test plans and coverage results, simplifying review even with non-technical managers.
· Re-use verification knowledge from pre-silicon to post-silicon, and from IP to SoC. You can use Trek to streamline IP verification as well. Or start right in at the SoC level. Trek works the way you want to.
Tests produced by Trek generate heavy, concurrent traffic and cover areas of your SoC that are unreachable by traditional means.
Trek stresses system functionality including:
· Data interactions between IP cores.
· Multiple IP cores running concurrently (by emulating cooperative multi-threading).
· Completion interlocks between IP cores (using polling or interrupts).
· Multiple concurrent interrupts.
· Memory coherency (by aggressive address selection and buffer shuffling tests). Trek creates a closed-loop, self-contained test environment using your existing testbench. You can test I/O dependencies at runtime: simply generate a Trek test, and the TrekBox takes care of the details such as putting the required input data at the right port at the right time during the test.
Human-friendly C code for easy debugging
Trek-generated tests are human-friendly C code, readable and understandable. Have a look at the sample: ample comments let you see exactly what was happening when a test failed. This makes for extremely easy debugging.
You can also work graphically in the Trek user interface, tracing the test path through the scenario model to identify:
· The behavior Trek was trying to create
· The pre-requisites Trek picked
· What was randomized and what was fixed Most importantly, the graph gives you a clear and simple view of the engineer's intent.
Free checking Because the expected results are built in to the scenario model, Trek automatically checks whether those expected results were achieved during testing.
Post-silicon validationUse Trek tests in the lab as well as your testbench. Get even more from Trek when you re-use your pre-silicon scenario models in post-silicon validation.