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Based on Calypto’s patented Sequential Analysis Technology, SLEC RTL functionally verifies sequential RTL optimizations that traditional formal technology tools can't, such as retiming and clock gating.
SLEC RTL finds design errors that other tools miss by formally comparing the functionality of the original RTL design and the corresponding optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC RTL does not require one to one mapping of registers.
SLEC RTL is being used by ARM licensees to validate sequential changes being made to the RTL version of the ARM cores. SLEC RTL gives ARM customers an automatic way to verify the functional intent of the RTL has not been compromised.