TDS by TSSI

Back End Design

Product Description

The (Test Development Series) TDS is the perfect tool for converting core-level test patterns provided by ARM into chip-level programs that can be targeted to major automatic test equipment (ATE). An interactive flow diagram tool can be used to create an repeatable, automated process for remapping test access to the chip-level without the need for ad-hoc Perl scripting. The tool handles STIL, WGL, EVCD, and other test languages. TDS handles both scan-based and functional patterns. Patterns are both error-checked and optimized.

Thorough verification is achieved by creating a simulation environment that models the device, test program, and ATE. Cadence, Mentor Graphics, and Synopsys simulation environments are supported.

TDS

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• VFP9-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• VFP10
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A5
• Cortex-A53
• Cortex-A57
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-M4
• Cortex-R4
• Cortex-R5
• Cortex-R7
• SC000
• SC100
• SC200
• SC300
• ARMv4
• ARMv5
• ARMv6
• ARMv7
• ARMv8
• StrongARM
• XScale
• Mali55
• Mali-200+GP2
• Mali-400
• Mali-T604
• Other

System IP

• Debug
• Interconnect Fabric
• Level 2 Cache Controller
• Memory Controller

Physical IP

• DDR I/O (DDRI/II)
• General Purpose I/O (Inline / Staggered)
• Register File Memory Compilers
• Specialty I/O (HSTL, SSTL)
• SRAM Memory Compilers
• Standard Cell Libraries

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