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TestBench XPress (TBX) co-modeling software application makes Veloce a transaction-level modeling (TLM) verification engine running up to 10,000x the speed of TLM software simulators.
TBX establishes a SCE-MI compliant, transaction-level communications link between testbenches running on a host system and an SoC modeled in Veloce. By accelerating both block-level and full-SoC regression tests, Veloce and TBX significantly reduce development schedule risks while leveraging TLM used during simulation.
In co-modeling, reusable testbenches are interfaced to synthesizable transactors collocated with the DUT in Veloce. These “accelerated” transactors convert high-level transactions to signal-level stimuli to drive the DUT.
The primary transaction modeling constructs of TBX are SystemVerilog DPI exported and imported tasks. This makes it straightforward to use Mentor supplied transactors or develop your own. TBX automatically generates a direct communication interface between the C/C++ or SystemC environment on a host and the SoC DUT in the Veloce emulator. With SystemVerilog testbenches, TBX executes the testbenches using the Questa simulator on the host PC.