Veloce accelerates block and full SoC RTL simulations during all phases of the design process. Veloce enables pre-silicon testing and debug at hardware speeds, using real-world data, while both hardware and software designs are still fluid.
• Improves end product quality by increasing the total verification cycles on the design before committing to silicon prototypes
• Reduces silicon spins due to functional problems by enabling full-system integration testing before first silicon
• Moves software off the project’s critical path by allowing debugging on emulated hardware early in the design process
The Veloce product family includes:
• Scalable verification platforms with capacities from 6 million up to 400 million gates
• Common configuration and debug software across the Veloce family
• Simulator-like debug environment
• 100% internal DUT visibility
• Network accessible, multi-user systems
Veloce delivers many software and application solutions that enable a comprehensive verification environment for chip and system level verification.
• TestBench XPress software enables transaction-based, co-emulation verification with support for untimed C/C++, SystemC, and SystemVerilog testbenches
• iSolve solutions, delivered as physical hardware-based products, provide application and protocol-based solutions for several vertical market areas; including video/audio, networking, wireless, embedded software, and storage
• Virtual Device software solutions provide host and peripheral models in a “virtualized” form for greater flexibility and visibility over a target protocol in applications such as video/audio, storage, and networking
• Veloce Transactors deliver transaction-based models for standard bus protocols to ease the transition from simulation to acceleration
• Advanced methodology support of UVM, OVM, VMM, TLM, etc.
• Assertion-based verification support in Veloce provides the same advanced capabilities as simulation for QVL, SVA, OVL, and PSL
• Connections to software development tools through physical and virtual JTAG solutions
• Integrations with Electronic System Level (ESL) tools using Vista with Veloce
• Highly productive, software-driven hardware verification using Codelink with Veloce
• Low power verification
Veloce hardware and software solutions allow design teams to quickly create reconfigurable hardware representations of new SoC designs and leverage verification investments across the project. This reduces the risk of design flaws in pre-silicon testing by verifying the SoC’s compliancy and interoperability with industry-standard protocols, thus reducing overall project schedules and costs.