TFT LCD Controller IP Core (AXI4) by Digital Blocks, Inc.

SoC IP Provider

Product Description

The Digital Blocks DB9000AXI4 TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 4.0 AXI4 Protocol Interconnect to a TFT LCD panel. The DB9000AXI4 contains a selectable 256 / 128 / 64 / 32-bit AXI4 Master Interface and uses the AXI4 higher burst lengths & Quality of Service (QoS) capabilities to target higher resolution, higher color depth TFT LCD panels, with their resulting high frame buffer memory data bandwidth & bounded latency requirements.

The DB9000AXI4 supports ASIC, ASSP, Xilinx, & Altera devices that support the AXI4 interconnect fabric.

TFT LCD Controller IP Core (AXI4)

Market Segment(s)

• Embedded
• Home
• Mobile
• Mobile Computing

Target Platform(s)

• Android
• Linux
• OpenGL ES
• OpenVG
• Windows Embedded CE

Companion Processor(s)

• Multimedia

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• VFP9-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A5
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-M4
• Cortex-R4
• Cortex-R5
• SC100
• ARMv4
• ARMv5
• StrongARM
• XScale
• Mali55
• Mali-200+GP2
• Mali-400
• Mali-T604

System IP

• Debug
• Interconnect Fabric

Physical IP

• DDR I/O (DDRI/II)
• General Purpose I/O (Inline / Staggered)
• Register File Memory Compilers
• SRAM Memory Compilers
• Standard Cell Libraries

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