Bit Block Transfer (BitBLT) 2D Graphics Engine IP Core (AXI4) by Digital Blocks, Inc.

Product Description

The Digital Blocks DB9100AXI4 Bit Block Transfer (BitBLT) Graphics Engine IP Core provides hardware acceleration of block moves with Raster Operation (256 data manipulation operations) of off-screen or on-screen data within frame buffer memory in a graphic display system. Additionally, the DB9100AXI4 provides hardware accelerated 2D graphics rendering support. Besides accelerated BitBLT & 2 D graphics operations, the DB9100AXI4 greatly increases software productivity.

The DB9100AXI4 supports ASIC, ASSP, Xilinx, & Altera devices that support the AXI4 interconnect fabric.

Bit Block Transfer (BitBLT) 2D Graphics Engine IP Core (AXI4)

Market Segment(s)

• Embedded
• Mobile Computing

Target Platform(s)

• Android
• Linux
• OpenGL ES
• OpenVG
• Windows Embedded CE

Companion Processor(s)

• Multimedia

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• VFP9-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• VFP10
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A15
• Cortex-A5
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-M4
• Cortex-R4
• Cortex-R5
• Cortex-R7
• SC000
• SC100
• SC200
• SC300
• ARMv4
• ARMv5
• ARMv6
• ARMv7
• StrongARM
• XScale
• Mali55
• Mali-200+GP2
• Mali-400
• Mali-T604
• Other

System IP

• Interconnect Fabric

Physical IP

• DDR I/O (DDRI/II)
• General Purpose I/O (Inline / Staggered)
• Register File Memory Compilers
• SRAM Memory Compilers
• Standard Cell Libraries