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Digital ADC technology can be implemented in a digital only silicon technology without using any of the analog IP blocks traditionally used for ADC designs. This reduces the design cycle time and cost of integrating ADCs in to ASICs, and can be implemented in fully digital microchips such as FPGAs avoiding the use of external costly ADCs and saving board space.
The analog input is optionally AC-coupled to adjust the DC bias, and then enters the FPGA or ASIC on the non-inverting input of an LVDS input buffer, where it is compared to the reconstructed feedback signal on the inverting input. The difference signal is processed by the digital logic to generate the feedback signal and the ADC output samples that can be used by the rest of the FPGA or ASIC.
The only other signal required by the Digital ADC is a clock input. The frequency of the clock and the characteristics of the tracking loop affect the bandwidth and signal-to-noise ratio of the Digital ADC.
* No analog block development required
* Shorter / lower risk design cycles
* Process / technology independent
* Digital layout
* Smaller silicon area
* Lower power consumption
* Suitable for applications requiring very low supply voltage
* Digital testing
* Extremely low offset drift
* Suitable for Rad-Hard environments
Additional key features:
* No missing codes
* Oversampling - reduces requirements for anti-aliasing filter