Cortex-R5 implementation by ac6-training

Product Description

Objectives
This course is split into 3 important parts:

Cortex-R5 architecture
Cortex-R5 software implementation and debug
Cortex-R5 hardware implementation.

Interaction between level 1 caches, TCM and main memory is studied through sequences.

The course explains how to assign access permissions and attributes to regions by using the MPU.

The exception mechanism is detailed, indicating how the VIC port can contribute to reduce interrupt latency.

Sequences involving memory, cache and external maste are used to explain the benefits of the ACP port.

The course also details the hardware implementation and provides some guidelines to design a SoC based on Cortex-R5.

An overview of the Coresight specification is provided prior to describing the debug related units.

Cortex-R5 implementation

Market Segment(s)

• General Purpose Products/Services

ARM Processor(s)

• Cortex-R5