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This course covers STM32F205, STM32F207, STM32F215, STM32F217 ARM-based MCU family
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This course has 5 main objectives:
- Describing the hardware implementation and highlighting the pitfalls
- Describing the ARM Cortex-M3 core architecture
- Becoming familiar with the IDE and low level programming
- Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
-.Describing independent I/O modules and their drivers.
- Note that this course has been designed from the architecture of the most complex STM32 F2-series device, the STM32F217.
Consequently, a chapter has been designed by Acsys for each possible integrated IP.
According to the actual reference chosen by the customer, some chapters may be removed.
- Products and services offered by ACSYS:
- ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
- ACSYS has also an expertise in FreeRTOS porting and uIP /LWIP stack or Interniche stack integration.
- A lot of programming examples have been developed by ACSYS to help the attendee to become familiar with the IDE he has chosen.
That is why the labs included in this course can be compiled and executed under 3 possible IDEs: IAR, Keil and GCC / Lauterbach Trace32.
A more detailed course description is available on request at email@example.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.
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Knowledge of ARM architecture is recommended.
. The following courses could be of interest:
.. USB Full Speed High Speed and USB On-The-Go, reference I6
.. Ethernet and switching, reference N1
.. IEEE1588, reference N2
.. CAN bus, reference I9
.. Memory cards, reference I18
ARCHITECTURE OF STM32F2XX MCUs
. ARM core based architecture
. Description of STM32F20X and STM32F21X SoC architecture
. Clarifying the internal data and instruction paths: AHB-lite interconnect,
. peripheral buses, AHB-to-APB bridges
. Integrated memories
. SoC mapping
THE ARM CORTEX-M3 CORE
. V7-M core family
. Core architecture
. Exception behavior, exception return
Basic interrupt operation, micro-coded interrupt mechanism
BECOMING FAMILIAR WITH THE IDE
Acsys covers 3 IDEs: Keil, IAR and GCC / Lauterbach
Thus the customer has just to indicate which one he has chosen
. Getting started with the IDE
. Parameterizing the compiler / linker
. Creating a project from scratch
. C start program
PROGRAMMING AND DEBUGGING
. Debug interface
RESET, POWER AND CLOCKING
. Power control
. Low power modes
. Bus matrix
. Power pins
. GPIO module
. System configuration controller
. External Interrupts
. Embedded flash memory
. Internal SRAM
. Flexible Static Memory Controller
. Advanced-control timers TIM1 and TIM8
. General-purpose timers (TIM2 to TIM5)
. General-purpose timers (TIM9 to TIM14)
. Basic timers (TIM6 and TIM7)
. Real Time Clock
. Independent Watchdog
. Window Watchdog
. 16-bit Analog-to-Digital Converter and Programmable Gain Amplifier
. 12-bit Digital-to-Analog Converter
SECURITY AND INTEGRITY
. CRC calculation unit
. Random Number Generation
. Hash processor
. Cryptographic processor
. Device Electronic Signature
CONNECTIVITY AND COMMUNICATION
. SPI in I2S mode
. bxCAN modules
. USB FS
. USB HS
. ISO7816 smartcard interface
. Digital camera interface