ARM’s highest performing processor, extending the capabilities of mobile and enterprise computing. Read More...
The LDPC encoder generates code words of the specified block length n for an binary information sequence of length k based on Parity Check Matrix (PCM) that has very low density of 1’s per rows and columns. The remaining elements of PCM are all 0’s. This LDPC has code rate of k/n and block length of n. The dimension of the PCM is (n-k)xk. The LDPC decoder IP core implements the min-sum-offset algorithm to decode LDPC codes. The core accepts soft information that is stored in memory and generates decoded information bits. The maximum number of iterations used in the decoding of LDPC codes is fed as input. Decoding is stopped when maximum iterations are reached or when code word is decoded without any errors.
1) Highly Flexible Architecture
2) Scalable to any block length LDPC Code Structure
3) LLR Computer for QAM-256 & QAM-1024, 6-bits
4) Very High Sustained Throughputs.
5) The Architecture is scalable for varying Parity Check Matrix density, code rates/lengths and LLR bit widths.
6) FPGA Validated IP Core.
7) Synthesized for ASIC Libraries
8) MoCA/G.hn/G.9960 Coaxial Communication Applications
9) DVB-S2, DMB-T/H Digital Video Broadcasting Applications
10)Storage/Flash Drive Read Channels Applications
11)WiMax/WLAN/WiGig Wireless & 10Gbase-T Applications.
The ARM interface is used for configuring several modes of the IP Cores. As this LDPC core supports applications involving very high sustained throughputs, ARM cores alone may be the embedded processor of choice for these SOCs.