Posedge Universal Flash Controller by Posedge Inc

SoC IP Provider

Product Description

The Posedge Universal Flash Controller (UFC) is a flexible high performance Soft IP core capable to  interface with NAND, NOR, Serial Flash and SRAM devices conforming to the latest Open NAND Flash Interface Working Group standards (ONFI 2.2). It has a very generic and modular architecture with AXI/AHB/APB/FIFO interfaces to meet various customer specific requirements. The UFC core internally AHB/AXI slave interface to connect to SoC and Serial peripheral, NAND, NOR industry standard interfaces towards the Flash memory. The data transfer between external flash or serial devices and the flash controller is through the register I/O or using DMA. The UFC can work up to 50 MHz of serial interface and up to 100 MHz on the Nand interface. To ensure less overhead for the Host Processor controlling the data transfers, multiple commands can be queued. The Controller can queue up to 16 commands and will have 16 deep data buffers for data transfer. The architecture ensures to easily meet timing at all the interfaces.
 

Features

NOR Flash Interface
• NOR Flash Interface supporting generic asynchronous memory
• Customizable to Compact Flash
• Programmable Setup, Access, Hold and Transition times
• Can address up to 256 MB and 8/16-bit bus

NAND Flash Interface
• Compliant to ONFI2.2
• Compliant to AMBA AHB, APB 2.0
• Supports different formats including but not limited to Samsung, Hynix
• Highly configurable for command and data cycles

ONFI2.2 Features
• Supports Asynchronous [0-5] and Synchronous [0-5] mode of operation
• Supports Interleaved read Operations
• Supports Interleaved Page Program and Erase Operations
• Supports Multiple LUN Operations
• Supports all mandatory commands and most of the optional commands
• Complete Access to Spare Area
• Customizable boot options

SRAM Interface
• Supports 8, 16 or 32 bits SRAM
• Supports device paced devices
• Performance single, fixed and variable bursts on SRAM

Serial Flash Interface
• SPI master interface at 50 MHz
• Supports Dual SPI and QUAD SPI mode
• SPI Boot Support
• SPI DMA mode for data transfers
• Progrmmable Command Sequence
• Master Clock derived from the AHB (System) Clock
• Supports mode 0, mode 3
• Programmable CPOL, CPHA
• Individually Controllable pins to drive chip-select , write protect and hold signals
• The IP can be configured to have 4 to 16 Command/Data buffers
• Configurable to be AHB or APB bus
• System Interface at 50-300 MHz

Slave Interface
• Configurable Command/Data buffer
• Thresholds to generate interrupts
• Configurable to be AXI,AHB or APB bus
• Control and Status Registers to configure the modules
• Transmit buffer (512 bytes) is parameterizable
• Receive buffer (512 bytes) is not parameterizable
• Programmed IO Mode (PIO) Data Transfer

Master Interface
• Supports Advanced High Performance Bus (AHB)
• Supports Single, INCR4, INCR8, INCR16 Burst mode of Operation
• Supports all slave device responses
• DMA used for Boot Code and Data transfer

Data Transfer
• Programmed IO mode
• DMA mode

Configuration
• Programmable page size – 512B, 2KB, 4KB, 8KB, 16KB
• Configurable FIFO Depth - typical (256 x 32)
• Support ECC Enable and Disable Option
• Programmable Access Timing
• Programmable Row (1-4Bytes) and Col Address Cycles (1-4Bytes)

Error Correction Codes (ECC)
• Supports Hamming Code (1 bit error correction and 2 bit error detection)
• Supports BCH Code (up to 40 bit error correction)

Boot Mode
• Customizable boot options
• DMA for boot code transfer
• Boot from NAND/SRAM/SPI-supported

Block Level Design Features
• Two Clock based design
• AXI/AHB/APB interface side works on system clock and Flash interface side works on flash clock

Advantages
• One engine supports multiple devices
• Lowest Gate count
• Complete Solution- IP, HW & SW , Development Kit
• Lowest Power/Highest Performance at System Level
• Scalable Architecture
• Multiple Interface Options
• Application Level Expertise
• World class professional support

Deliverables
• Fully Synthesizable Verilog RTL 
• Unencrypted Source Code
• Self-checking Testbench and Test cases
• Verification specification
• User documentation
• Integration manual
• Simulation Scripts – NC-Verilog , VCS, Model Questa
• ASIC/FPGA synthesis scripts

 

Posedge Universal Flash Controller

Market Segment(s)

• Embedded
• Home
• Mobile

Target Platform(s)

• Android
• Linux
• Symbian
• VxWorks

Companion Processor(s)

• Flash

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM946E-S
• ARM966E-S
• ARM968E-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A5
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-M4

System IP

• Interconnect Fabric

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