Cortex-M1 implementation by ac6-training

Product Description

This course covers the Cortex-M1 ARM core targetting FPGA SoCs


Objectives
This course is split into 3 important parts:

Processor architecture

Software implementation

Hardware implementation.


A tutorial has been developed by ACSYS to facilitate the understanding of Cortex-M1 low level programming, therefore labs can be replayed after the course.

The course explains how to design a SoC based on Cortex-M1, clarifying the operation of the interconnect and the debug facilities integrated in the CPU.

Labs can be run under 2 possible environments: Eclipse/RVDS or Keil IDE
For open courses, labs are run under Eclipse/RVDS.


A more detailed course description is available on request at info@ac6-training.com

Prerequisites
Knowledge of ARM7/9.

This course does not include chapters on low level programming.

ACSYS offers a large set of tutorials to become familiar with RVDS, assembly level programming, compiler hints and tips.


More than 12 correct answers to Cortex-R prerequisites questionnaire.

Plan

First day
ARM Cortex-M1 INTRODUCTION
ARM Cortex-M1 CORE
EXCEPTIONS
OVERVIEW OF THUMB-2 INSTRUCTION SET

Second day
INTERRUPTS
MEMORY TYPES
INVASIVE DEBUG
INTEGRATION

Third day
IMPLEMENTATION
AMBA3.0 INTERCONNECT SPECIFICATION
AHB - ADVANCED HIGH PERFORMANCE BUS
APB - ADVANCED PERIPHERAL BUS
AHB CORTEX-M1 PORTS

Cortex-M1 implementation

Market Segment(s)

• General Purpose Products/Services

ARM Processor(s)

• Cortex-M1