The CellMath Designer™ datapath synthesis tool is used by
designers to reduce area, improve performance and lower
power consumption for datapath-intensive design blocks.
CellMath Designer combines advanced synthesis techniques
with patented datapath architectures to reduce circuit area
and power and for circuit speeds difficult to achieve through
other means. CellMath Designer works in conjunction with
general logic synthesis products and allows designers to
quickly achieve better implementations of datapath-intensive
blocks using existing RTL code.
CellMath Designer is used in conjunction with ARM Logic IP to
target a broad range of ASIC process technologies.