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SystemC Modeling Services
CircuitSutra provides SystemC based modeling services to SoC / IC companies. The services include creating sftware model of the target system at various abstraction levels (Functional view, Programmers View, Architectural view, Verification view). These offerings will enable the ARM's customers to quick start their ESL activity.
We have demonstrated expertise in creating the virtual platform of ARM processor based SoC. Such a platform created by using ARM926 processor model is able to boot busybox embedded Linux in about 10 seconds, and the full debian linux with GUI support in about 30 seconds on a laptop that supports hardware acceleration. The platform can be used to boot any embedded OS and is suitable for embedded software development.
The virtual platform is created by stitching the models of IP blocks exposing the TLM interfaces, with the model of ARM processor core. The design is such that it can be integrated with the processor model from any source without requiring any change in the rest of the platform and IP models. We can use processor models from various sources: ARM Fast models from ARM, processor models from Open virtual platform (OVP), Qemu in box methodology defined by GreenSocs, or any other source).
The IP models are created by using OSCI TLM2.0 standard and can be plugged into any ESL environment.
The IP models are created using the STARC TLM guidelines. The communication and computation are separated so as to allow maximum code re-use across abstraction levels.
List of offerings
- SystemC based Electronic System Level (ESL) Design methodology
- Transaction Level Modeling (TLM) of IP/SoC at various abstraction levels
- Virtual Platform development services
----Platform for eSW development & testing
----Platform for architectural exploration
----Platform for RTL verification
----Platform for any other customized need
-Bus specific TLM Kit (By extending OSCI TLM2.0)
-Adaptors between different abstraction levels
-Standards based ESL / EDA tool independent models of IP blocks
Modeling standards supported:
OSCI TLM2.0, STARC TL Guidelines, OCP-IP TLM Kit
Closely following the upcoming standards:
OSCI: SystemC synthesizable subset
OSCI: SystemC AMS extensions
Abstraction Levels supported:
Data granularity: Transaction (TR), Bus Phase (BP), Bus Signal (BS)
Timing Abstraction: Untimed (UT), App. Timed (AT), Cycle Accurate (CA)
Our expertise covers the entire spectrum ranging from untimed models to the Cycle accurate models.
Use cases supported:
Embedded software development (UTTR, ATTR)
Architectural exploration, performance optimization etc.. (ATTR, ATBP)
RTL verification (CABS)