AH264-IP by Allegro DVT

Product Description

High-Profile/High-Definition Encoding IP

The high-profile design includes the most advanced H.264 coding tools. Using efficient compression tools like cabac entropy coding, dynamic transforms, enhanced intra prediction and scaling lists, Allegro’s H.264 encoding IP brings significant bit rates savings compared to existing solutions.

Allegro’s H.264 IP encoder design allows fast and easy integration in a wide range of System-On-Chip (SOC) applications thanks to is ARM AMBA bus ready connectivity for both data path, using an AHB or an AXI master interface, and control path, using either an APB or AXI slave interface.

The H.264 IP core is an independent entity, requiring minimum support from the SOC embedded CPU. The motion estimation algorithms have been optimized to fit the memory bandwidth and latency requirements of consumer SOCs.

Thanks to the product's hardware architecture, the H.264 coding IPs minimize both gate counts and power consumption.

AH264-IP

Market Segment(s)

• Home
• Mobile

Companion Processor(s)

• Multimedia

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A8
• Cortex-A9
• Cortex-M0
• Cortex-M1
• Cortex-M3
• Cortex-R4
• ARMv4
• ARMv5
• ARMv6
• ARMv7
• StrongARM
• XScale