
H.264 High-Profile/High-Definition Encoding IP
The AL-H264-E design includes the most advanced H.264 coding tools. Using efficient compression tools like cabac entropy coding, dynamic transforms, enhanced intra prediction, scaling lists, adaptive B pictures and direct mode, Allegro DVT’s H.264 encoding IP brings significant bit rates savings compared to existing solutions.
Allegro DVT’s H.264 IP encoder design allows fast and easy integration in a wide range of System-On-Chip (SoC) applications. The H.264 IP core is an independent entity, requiring minimum support from the SoC embedded ARM CPU. It is delivered with ARM AMBA bus ready connectivity for the data path (an AHB or an AXI master interface) and the control path (either an APB or AXI slave interface). The motion estimation algorithms have been optimized to fit the memory bandwidth and latency requirements of consumer SoCs. Thanks to its hardware architecture, the H.264 encoding IP minimizes both gate counts and power consumption.