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Vayavya Labs offers a suite of tools that help semiconductor &
embedded system design firms to reduce the time and effort
involved in embedded platform design, development and testing.
Our tools provide mechanisms to formally capture the 'Design
Intent' (Specifications) of IC and Embedded Software flows. These
specifications are used as input to a set of 'Intelligent
Generators' that help in automation of activities in design flows
there by reducing the time and effort.
Our flagship product; DDGen is used to generate the low level
driver software. Other tools in this suite are;
Brief description of the modules in this tool-suite are:
DDGen : An automated device driver generator
The tool helps to capture the device(IC) and software (run time)
specifications in a formal manner. These specifications are used
as input to the tool (DDGen) which helps in analysing the
specifications and device programming models. It further fits the
device programming model into the appropriate run time (including
operating systems) constraints. The end result, ANSI C compliant
device driver code that can be plugged into application
development! to demystify device driver development and speed up
your embedded product roll out Evaluate DDGen now.
RegGen: Register map RTL generator
This tools helps in automating the synthesizable RTL generation
(Verilog, SystemVerilog or VHDL code) for the register map files
that the architect and design teams define in a design flow.
Avoid hand coding of RTL and test bench for register maps in your
design to gain time and minimise efforts.
DocGen: Document generator
Quick generation of internal and customer document views. High
light the register map and programming features of the device to
target designers. Several formats (PDF, HTML, MS-Word) of
document views supported.(IC).
Some of the customer benefits by using these tools are;
1. Automate the device driver generation
2. Dramatically reduced debug efforts
3. Enforce Design-before-Code policy across your organization
4. Easy to Learn/Adopt/Maintain generated code
5. Industry endorsed IP-XACT based specification (with vendor