
- First behavioral-level formal analysis tool for verilog and
SystemVerilog
- Describe interface protocols and design properties using
behavioral-level testbench with minimal random
constraints,reference models, and properties vs complex RT -
level methods.
- Eliminate major development effort to write constraints
guiding coverage test generation for corner cases.
Support reference model based methodologies which greately
improve scalability of formal analysis.
- Tightly integrated simulation and formal engines provide
simulation-centric feel and better control over case analysis
and refinement.
- More efficient for both designers and verification engineers
Insight - Formal Analysis tool