DFI Compliant DDR2/3 PHY by Uniquify Inc.

SoC IP Provider

Product Description

DFI PHY Product Overview

Uniquify’s DDR PHY is a complete DFI compliant PHY solution that eliminates tough timing problems such as data / clock skew, setup / hold time, and complex physical implementation issues.

Patent-pending Self-Calibrating Logic (SCL™) technology ensures low read data capture latency and more system-level timing margins. Dynamic configuration of the PHY at power-up (or on-the-fly) compensates for system-level variations in operating conditions minimizes field failures, prevents test escapes in the field, and detects reliability problems that can crop up during extended periods of field operation.

DFI PHY Product Highlights

 DFI Compliant PHY Solution
 Patent-pending automatic Self-Calibrating Logic (SCL™) technology eliminates system level timing issues (on-the-fly support available)
 Low read data capture latency
 Ultra-low power design
 Uniquify’s PHY compiler customizes features and optimizes performance for your DDR application and design
 Flexibility in DDR I/O order
 Rectilinear shape supported by Uniquify’s ASIC Implementation
 Accelerated system bring-up time
 Chip / System yield improvement through SCL™ (Design for yield)
 Embedded chip / system testability (DFT support)
 Dynamic On-Die Termination control for DDR pads

DFI Compliant DDR2/3 PHY

Market Segment(s)

• Embedded
• Enterprise
• Home
• Mobile
• Mobile Computing

Companion Processor(s)

• Biometrics
• Communication
• DSP
• Flash
• Multimedia

ARM Processor(s)

• ARM7EJ-S
• ARM7TDMI
• ARM7TDMI-S
• ARM720T
• ARM920T
• ARM922T
• ARM940T
• ARM946E-S
• ARM966E-S
• ARM968E-S
• ARM1020E
• ARM1022E
• ARM1026EJ-S
• ARM1136J-S
• ARM1136JF-S
• ARM1156T2(F)-S
• ARM1176JZ(F)-S
• ARM11 MPCore
• Cortex-A8
• Cortex-A9
• Cortex-M0

System IP

• Interconnect Fabric

Physical IP

• DDR I/O (DDRI/II)

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