DFI PHY Product Overview
Uniquify’s DDR PHY is a complete DFI compliant PHY solution that eliminates tough timing problems such as data / clock skew, setup / hold time, and complex physical implementation issues.
Patent-pending Self-Calibrating Logic (SCL™) technology ensures low read data capture latency and more system-level timing margins. Dynamic configuration of the PHY at power-up (or on-the-fly) compensates for system-level variations in operating conditions minimizes field failures, prevents test escapes in the field, and detects reliability problems that can crop up during extended periods of field operation.
DFI PHY Product Highlights
DFI Compliant PHY Solution
Patent-pending automatic Self-Calibrating Logic (SCL™) technology eliminates system level timing issues (on-the-fly support available)
Low read data capture latency
Ultra-low power design
Uniquify’s PHY compiler customizes features and optimizes performance for your DDR application and design
Flexibility in DDR I/O order
Rectilinear shape supported by Uniquify’s ASIC Implementation
Accelerated system bring-up time
Chip / System yield improvement through SCL™ (Design for yield)
Embedded chip / system testability (DFT support)
Dynamic On-Die Termination control for DDR pads